Method and system for loading FPGA target program

A target program and programming logic technology, applied in the field of data communication, can solve problems such as inability to upgrade online and long loading time, and achieve the effect of convenient maintenance and saving startup time

Inactive Publication Date: 2007-03-14
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In order to solve the problems of long loading time and inability to upgrade online in the prior art, the present invention provides a method and system for loading FPGA target programs

Method used

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  • Method and system for loading FPGA target program
  • Method and system for loading FPGA target program
  • Method and system for loading FPGA target program

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0062]Referring to Figure 1, a piece of FLASH is plugged on the EPLD of the single board, and two FPGA chips are connected to the EPLD through the bus at the same time, and the two FPGA chips are connected in parallel. In this embodiment, there are two FPGA chips on the business processing single board to realize the large-scale business processing logic of the single board. It is required to realize fast loading of the two FPGA chips when the single board is powered on and to realize online upgrade of the system. .

[0063] Here we take the FPGA target program size as 2.11MB as an example to illustrate, then the single board design EPLD is plugged with a 4MB FLASH to store the FPGA target program. Since the logic functions of the two FPGAs on the single board are exactly the same, the EPLD adopts parallel and bus The way to load the FPGA.

[0064] Referring to Fig. 2, the present invention provides a kind of method of loading FPGA target program, comprises the following step...

Embodiment 2

[0076] The main control board upgrades the target program in FLASH online through the interface of HDLC to Local Bus (local bus) and FLASH. After the online upgrade is completed, when the target program of the FPGA logic needs to be updated, the main control board sends a reload command, and the EPLD will start The FPGA loads the state machine to update and load the logic of the FPGA. If the target program of the FPGA logic does not need to be updated temporarily, reloading may not be performed.

[0077] The main control realizes online programming of FLASH through HDLC short frame paging, and EPLD realizes the conversion of HDLC to Local Bus and FLASH interface. Short-frame paging loading means that the capacity of each page is 128B. Divide the address of FLASH into three sections: Flash_addr[21:15], Flash_addr[14:7] and Flash_addr[6:0]. Set the HDLC writable register inside the EPLD. When HDLC performs a write operation on Flash, first write the FLASH The high address of t...

Embodiment 3

[0112] After the target program in FLASH is upgraded, when the FPGA target program needs to be updated, the main control board issues a reload command, and the EPLD will start the FPGA loading state machine, see Figure 6. The specific update and loading process includes the following steps:

[0113] Step 301: After the update of the target program in the FLASH is completed, the main control board sets the reload (heavy load) signal to "1", when the reload is set to "1", the EPLD logic enters the PROG_START state, and clears the reload in the PROGSTART state.

[0114] Steps 302 to 305 are the same as steps 102 to 105 to reload the FPGA, until the loading is complete and return to the IDLE state. I won't go into details here.

[0115] When two FPGAs are selected and loaded at the same time, the FPGA code is 2.11MB, the clock cycle is 1 / 6.25MHz=160ns, the time required for parallel input is 2.11MB×160ns, other states need about 5 cycles, and the FPGA STARTUP process takes about 5...

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Abstract

The provided method for loading FPGA object program comprises: externally hanging flash memory on single-board EPLC to store the FPGA object program; configuring single-board interface; electrical resetting, loading the program into FPGA. This invention implements automatic loading to save startup time, and can on-line update for maintenance.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a method and system for loading an FPGA target program. Background technique [0002] Nowadays, more and more business processing single boards use FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips to realize business processing functions, and the logic scale is also increasing. Load time requirements are also getting faster. Several existing loading methods cannot well meet the design requirements due to the need to increase the CPU or the loading time is too long. [0003] CPU loading is a loading method commonly used by single boards. This method includes the FPGA target program in the host software. After the system starts, the CPU executes the program and loads the target program into the FPGA. [0004] The disadvantages of this method are: 1) the loading time is long, usually more than ten seconds, and the larger the scale of the target program, t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445
Inventor 侯雪华
Owner HUAWEI TECH CO LTD
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