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Semiconductor storage device

一种存储装置、半导体的技术，应用在半导体器件、信息存储、静态存储器等方向，能够解决单元读出速度变慢等问题，达到提高读出速度、提高读出宽裕量、提高自由度的效果

Inactive Publication Date: 2007-04-04
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if the third diffusion region 221 is used as a common power source, the speed at the time of cell readout may be slowed down.

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
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Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0067] The semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a partial plan view schematically showing the configuration of a semiconductor memory device according to Embodiment 1 of the present invention. 2 is a partial cross-sectional view along line X-X' (of FIG. 1 ) schematically showing the configuration of the semiconductor memory device according to Embodiment 1 of the present invention. 3 is a partial cross-sectional view along line Y-Y' (of FIG. 1 ) schematically showing the configuration of the semiconductor memory device according to Embodiment 1 of the present invention.

[0068] The semiconductor memory device according to Embodiment 1 is a nonvolatile semiconductor memory device that stores 2-bit information per cell. The semiconductor storage device has: a substrate 1, an insulating film 2, a first selection gate 3a, a second selection gate 3b, an insulating film 4, an insu...

Embodiment approach 2

[0145] Next, a semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. 23 is a partial cross-sectional view schematically showing the structure of a semiconductor memory device according to Embodiment 2 of the present invention. 24 to 26 are process cross-sectional views for explaining the manufacturing method of the semiconductor memory device according to Embodiment 2 of the present invention.

[0146] In the semiconductor storage device according to Embodiment 2, the ON cell (the floating gate below the second control gate 11 b and the third control gate 11 c in FIG. 1 ) in the bypass section of the semiconductor storage device according to Embodiment 1 The configuration of the cell in the ON state (erased state) in pole 6 is different. Referring to FIG. 23, in the semiconductor memory device according to Embodiment 2, in the ON cell of the bypass portion, the second control gate 11b and the floating ...

Embodiment approach 3

[0159] Next, a semiconductor memory device according to Embodiment 3 of the present invention will be described with reference to the drawings. 27 is a partial cross-sectional view schematically showing the structure of a semiconductor memory device according to Embodiment 3 of the present invention. 28 is a cross-sectional view illustrating the steps of the method of manufacturing the semiconductor memory device according to Embodiment 3 of the present invention.

[0160] In the semiconductor storage device according to Embodiment 3, the ON cell (the floating gate below the second control gate 11 b and the third control gate 11 c in FIG. 1 ) in the bypass section of the semiconductor storage device according to Embodiment 1 In pole 6, the configuration of the cell in the ON state (erased state) is different. Referring to FIG. 27 , in the semiconductor memory device according to Embodiment 3, the ON cell of the bypass portion has a structure in which the floating gate under t...

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PUM

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Abstract

A semiconductor storage device in which product cost is reduced comprises: a memory cell section (cells belonging to Wni-1, WOi-Wni) and a bypass section (cells belonging to BWOi, BWOi-1, BWli, BWli-1). The memory cell section has a select gate (3a), floating gates (6), a first diffusion region (7a), a second diffusion region (7b) and a first control gate (11a). The bypass section comprises: the select gate (3a), the first diffusion region (7a), the second diffusion region (7b) and a second control gate (11b). The second control gate (11b) controls a channel in an area between the select gate (3a) and the first diffusion region (7a), or between the select gate (3a) and the second diffusion region (7b). The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

Description

technical field [0001] The present invention relates to a semiconductor memory device having cell transistors, and more particularly to a semiconductor memory device that stores information of multiple bits per cell. Background technique [0002] Among conventional semiconductor memory devices, a nonvolatile semiconductor memory device having a cell transistor as shown in FIG. 38 (conventional example 1) is known as a nonvolatile semiconductor memory device that stores information of multiple bits per cell. In the nonvolatile semiconductor memory device according to Conventional Example 1, there are two strip-shaped conductivity-type opposite regions 123a, 123b, which are formed on the semiconductor base 121 with a conductivity-type strip-shaped semiconductor layer 124a sandwiched between them. On the surface layer; the first floating gate 127a, which is formed from the top of one conductivity type opposite region 123a to one side surface of the semiconductor layer 124a thro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115
CPCG11C16/0491H01L27/11521H01L29/42324H01L27/115H01L29/7885H10B69/00H10B41/30
Inventor 须藤直昭金森宏治真田和彦
Owner NEC ELECTRONICS CORP