Non-volatile memory body and operating method and mfg. method thereof

Abstract

The invention relates to a nonvolatile memory body and the operating and making methods thereof. And it comprises channeled substrate, charge capturing trap layer in the channel, gate in the channel isolated from the substrate at least through the charge capturing trap layer, and source / drain region in the substrate on two sides of the channel, where the gate material comprises p-doped semiconductor material so as to make it especially suitable to erase the memory body by gate electric hole injection mechanism.

Description

technical field [0001] The present invention relates to a non-volatile memory, and in particular to a non-volatile memory with a charge trapping layer, as well as its operating method and manufacturing method. Background technique [0002] Charge-trapping non-volatile memory has been extensively studied recently because of its simplified manufacturing process and the fact that each memory cell can have more than one storage location. For example, Eitan et al. (IEEE EDL 2000, Vol.21, No.11, 543-545) proposed a local trap type metal oxide semiconductor (MOS) structure binary non-volatile memory cell, which has an n-type The gate electrode and a silicon oxide / silicon nitride / silicon oxide (ONO) compound layer located between the substrate and the gate electrode, wherein the silicon nitride layer is used as a charge trapping layer. However, since the channel length of this kind of memory cell is very small, it will cause serious breakdown leakage and second-bit effect. [0003...

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Problems solved by technology

This article also teaches the method of erasing the memory cell by using the substrate-to-charge-trapping layer-to-band thermoelectric hole tunneling mechanism (BTBHHT). The charge is easy to leak

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