Clock and data recovery circuit

Abstract

There is provided a clock data reproduction circuit capable of improving the following speed following the reception data signal fluctuation and the clock quality as well as automatically performing adjustment to an optimal identification phase. The clock data reproduction circuit includes: a first feedback loop (204) having a phase comparator (209) for inputting clock from a VCO (203) and a reception data signal and detecting a phase difference, an integration circuit (210), and the VCO (203); and a second feedback loop (207) having an identifier (205) for inputting a reception data signal (201), a phase comparator (211) for inputting the output from the identifier (205) and the reception data signal (201) and detecting a phase difference, an integration circuit (212), and a phase shifter (208) for inputting the clock outputted from the VCO (203), shifting the phase according to the integration output of the integration circuit (212) when outputting it.

Description

technical field [0001] The present invention relates to a clock data regeneration circuit for identifying / regenerating an input data signal by regenerating a clock for identification from a data signal. Background technique [0002] Such a conventional clock data regeneration circuit will be described below. FIG. 8 is a diagram showing a configuration of a clock data regeneration circuit disclosed in Non-Patent Document 1 described later. If referring to Fig. 8, then this clock data regeneration circuit, possesses: compare the phase of two input signals, the phase comparator (Phase Detector) 602 that outputs comparison result; The integration circuit 603 that phase comparison result signal is integrated; The output voltage of the circuit 603 is a voltage controlled oscillator (Voltage Controlled Oscillator: abbreviated as “VCO”) 604 whose oscillation frequency is variable, and these constitute a feedback loop (feedback loop) 601 . The integrating circuit 603 is constituted...

AI Technical Summary

Problems solved by technology

[0021] However, in the above configuration, there is a problem that, as shown in FIG. 12( a ), since the response time of the output of the integrating circuit (VCO control signal) to data fluctuations becomes longer, as shown in FIG. 12( b ), , the clock data regeneration circuit cannot immediately track the instability or fluctuation of the transmission data signal, so the time until the correct clock is output again and the data regeneration becomes longer

[0022] On the other hand, when the time constant of the integrating circuit is reduced in order to shorten the response time, there is a problem that, as shown in FIG. Deviation of synchronization or increase in phase noise

Usually, this delay time greatly affects the transmission data rate or the circuit configuration, so it is difficult to set the optimum circuit constants

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