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Method and apparatus for exchanging the contents of registers

a register and register technology, applied in the field of digital computer systems, can solve the problems of consuming three times as many clock cycles, wasting valuable space, and a bottleneck in the stack,

Inactive Publication Date: 2004-04-08
SAFFORD KEVIN DAVID +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention is a computer system that can execute move instructions in parallel using a register stack and dependency checking logic. The system can also detect and address stack underflow exception, which allows for the execution of move instructions without a stack underflow exception. The technical effect of this invention is improved performance and efficiency in executing move instructions."

Problems solved by technology

This creates a "bottleneck" in the stack.
But, at least one problem with register renaming is that it requires that the pointers be stored in additional hardware which adds to the cost and complexity of the system as well as consuming valuable space.
This method of emulation, with its three micro-code instructions, consumes three times as many clock cycles as the single FXCH instruction and, in some cases, may consume even more, depending upon the latency associated with the move operations.

Method used

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  • Method and apparatus for exchanging the contents of registers
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  • Method and apparatus for exchanging the contents of registers

Examples

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Embodiment Construction

[0017] A. Description of an Embodiment

[0018] FIG. 1 illustrates a computer system 10 in which the present invention may be implemented. The computer system 10 comprises at least one processor 20, main memory 30, and various interconnecting data, address, and control bases (numbered collectively as 40). An instruction set 50 (which may be a guest instruction set) and an operating system 60 may be stored in main memory 30. As illustrated in FIG. 2, the processor 20 comprises a floating point unit 70, dispatch or dependency checking logic 80, at least two execution units 90a and 90b, micro-code ROM 100, a register stack 120 (in this embodiment the register stack 120 comprises eight individual registers 120(0)-(7)), a floating point tag word (FPTW) register 130, and various busses and interconnections (numbered collectively as 110). (One skilled in the relevant art will note that there need not be a separate floating point unit--the execution units are equally capable of executing float...

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PUM

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Abstract

A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined whether a stack underflow exception has occurred and if it has, the move instructions can be flushed, and a micro-code handler algorithm invoked that operates to allow execution of the move instructions in parallel without a stack underflow exception.

Description

I. FIELD[0001] The present invention relates to digital computer systems, and more particularly, but not by way of limitation, to methods and apparatus for executing instructions in such systems.II. BACKGROUND[0002] In x86 computer systems, the floating point unit (FPU) comprises a plurality of data registers. Floating point instructions treat this plurality of data registers as a register stack. All addressing of the data registers is relative to the register on the top of the stack. The register number of the current top-of-stack register is stored in a stack TOP field. Thus, load operations decrement TOP by one and load a value into the new top-of-stack register, while store operations store the value from the current top-of-stack register in memory and then increment TOP by one.[0003] Many floating point instructions, however, only operate on the top one or two registers of a register stack. Thus, if the desired information is located in, e.g., the fourth stack register, one or ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/30G06F9/315G06F9/318G06F9/38
CPCG06F9/30032G06F9/3885G06F9/3861G06F9/30174
Inventor SAFFORD, KEVIN DAVIDKNEBEL, PATRICK
Owner SAFFORD KEVIN DAVID
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