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Nonvolatile semiconductor memory device

a semiconductor memory and non-volatile technology, applied in static storage, digital storage, instruments, etc., can solve the problems of reducing the operation speed, increasing the number of depleted memory transistors, and erroneous reading, and achieve the effect of little variation in erasing tim

Inactive Publication Date: 2005-03-17
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a nonvolatile semiconductor memory device with little variations in erasing time without causing depletion in memory transistors. This is achieved by a combination of a reference transistor and a memory transistor, with a read circuit, a comparison circuit, and a data signal rewriting circuit. The reference transistor has its threshold voltage set to a reference voltage between the first and second voltages, while the memory transistor has its threshold voltage set to the first and second voltages for storing data signals at different logic levels. The read circuit reads the threshold voltage of the reference transistor, the comparison circuit compares it with the reference voltage, and the data signal rewriting circuit supplies a pulse signal train to change the threshold voltage of both transistors. This prevents depletion of the memory transistor and reduces variations in erasing time. The pulse waveform instruction signal is generated based on the threshold voltage of the memory transistor and the reference transistor, and the amplitude voltage of the pulse signal train is increased and decreased in response to the threshold voltage of the memory transistor.

Problems solved by technology

In such a flash memory, if the erasing condition is weak, it takes longer time to erase data, thereby reducing the operation speed.
On the contrary, if the erasing condition is too strong, the threshold voltage is excessively decreased to cause an increased number of depleted memory transistors, thereby resulting in erroneous reading.
In this erasing method, however, variations in erasing time between chips or memory blocks cannot be reduced.
In addition, the erasing time is long.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0031]FIG. 1 is a cross sectional view showing a configuration of a memory transistor 1 of a flash memory in accordance with a first embodiment of the present invention. In FIG. 1, this memory transistor 1 includes a floating gate 2 formed above a surface of a well W at a semiconductor substrate with an insulating layer interposed, a control gate 3 formed thereabove with an insulating layer interposed, and a source 4 and a drain 5 formed on the well W surface on the opposite sides of gates 2, 3, respectively. Prescribed voltages VW, VG, VS, VD are applied to well W, control gate 3, source 4, and drain 5, respectively. Threshold voltage VT of memory transistor 1 varies depending on the number of electrons in floating gate 2.

[0032] In a reading operation, as shown in FIG. 2A, 1V is applied to drain 5 of memory transistor 1, 3.3V is applied to control gate 3, and 0V is applied to source 4 and well W, so that it is determined whether a current ID between drain 5 and source 4 exceeds a ...

second embodiment

[0059]FIG. 10 is a circuit block diagram showing a part in connection with data erasing in a flash memory in accordance with a second embodiment of the present invention, in contrast with FIG. 6. Referring to FIG. 10, read circuit 10 detects threshold voltage VT of memory transistor 1 selected by decoder 7. Read circuit 11 detects threshold voltages VTR1, VTR2 of two reference transistors 6 selected by decoder 8. Threshold voltage VTR1 is set at a voltage (for example 5.0V) between the threshold voltage (7.5V) of memory transistor having data “0” written and the threshold voltage (2.7V) of memory transistor 1 having data “1” written. Threshold voltage VTR2 is set at a voltage (2.8V-3.2V, for example 3.0V) slightly higher than the threshold voltage (2.7V) of memory transistor 1 having data “1” written.

[0060] Comparator 12 compares threshold voltage VT of memory transistor 1 detected by read circuit 10 with threshold voltage VTR1 of reference transistor 6 detected by read circuit 11,...

third embodiment

[0072]FIG. 14 is a block diagram showing a main part of a flash memory in accordance with a third embodiment of the present invention, in contrast with FIG. 6. Referring to FIG. 14, the present flash memory differs from the flash memory in FIG. 6 in that reference block RBLK is omitted, two read circuits 10, 11 are connected together to memory block BLK through decoder 7, and comparator 12 is replaced with two comparators 17 and 18.

[0073] In this flash memory, one memory transistor 1 preliminarily selected from a plurality of memory transistors 1 belonging to memory block BLK is uses as reference transistor 6. In the erasing operation, threshold voltage VTR of reference transistor 6 is decreased together with threshold voltage VT of all the memory transistors 1 in memory block BLK as the erasing target.

[0074] Read circuit 10 detects threshold voltage VT of memory transistor 1 selected by decoder 7. Read circuit 11 detects threshold voltage VTR of reference transistor 6 selected by...

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Abstract

In a flash memory, a threshold voltage of a memory transistor is decreased quickly by increasing a rising speed of a pulse voltage of an erasing pulse signal train during the first period of an erasing operation. In response to the threshold voltage of the memory transistor becoming lower than a threshold voltage of a reference transistor, the threshold voltage of the memory transistor is decreased slowly by reducing the rising speed of the pulse voltage of the erasing pulse signal train. Therefore, the erasing time can be reduced and depletion of the memory transistor can be prevented.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a memory transistor having a floating gate. [0003] 2. Description of the Background Art [0004] Conventionally, in a flash memory, data is written by injecting electrons into a floating gate of a memory transistor and setting a threshold voltage of the memory transistor high (storing data “0”), while data is erased by removing electrons from the floating gate of the memory transistor and setting the threshold voltage of the memory transistor low (storing data “1”). [0005] In such a flash memory, if the erasing condition is weak, it takes longer time to erase data, thereby reducing the operation speed. On the contrary, if the erasing condition is too strong, the threshold voltage is excessively decreased to cause an increased number of depleted memory transistors, the...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C11/34G11C16/10G11C16/28G11C16/34
CPCG11C16/10G11C16/3445G11C16/344G11C16/28
Inventor NITTA, FUMIHIKOKOBAYASHI, SHINICHI
Owner RENESAS ELECTRONICS CORP