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Apparatus and method for electrolytically depositing copper on a semiconductor workpiece

a technology of electrolysis and workpieces, applied in the direction of electrical apparatus, superimposed coating process, coating, etc., can solve the problems of low sheet resistance of copper layers that are electroplated in the disclosed manner, and easy annealing, etc., to achieve excellent conformal copper coating, and good uniformity

Inactive Publication Date: 2005-07-14
SEMITOOL INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"This patent describes a new method for coating semiconductor workpieces with copper using an alkaline electrolytic copper bath. This method allows for the formation of a conformal coating that fills microstructures in the workpiece. The resulting coating has low sheet resistance and can be annealed at low temperatures. The method can be used in various steps in the manufacturing process of metallization layers in workpieces. Additionally, the patent describes a process for enhancing a seed layer by depositing additional metal thereon in a separate deposition step to provide an enhanced seed layer that is suitable for use in a primary metal deposition. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece. The patent also describes plating solutions for blanket plating, fill-plating of recessed micro-structures, and improving the resistivity of the resulting copper film."

Problems solved by technology

Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Method used

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  • Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
  • Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
  • Apparatus and method for electrolytically depositing copper on a semiconductor workpiece

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example 1

[0068] Comparison of Acid Copper Plating with and Without Seed Layer Enhancement

[0069] Semiconductor wafers 1, 2 and 3 were each coated with a 200 Angstrom PVD copper seed layer. In accordance with the present invention, wafers 1 and 2 had seed layer enhancement from citric acid and EDTA baths, respectively, the compositions of which are set forth below: [0070] Bath for Wafer 1: 0.1 M Cu SO4+0.2 M Citric acid+0.05 M H3B03 in D.I. water at pH 9.5, temperature 25° C. [0071] Bath for Wafer 2: 0.1 M Cu SO4+0.2 M EDTA acid+0.05H3BO3 in D.I. water at pH 12.5, temperature 25° C.

Wafer 3 did not have any seed layer enhancement.

[0072] The three wafers were then plated with a 1.5 micron copper layer from an acid copper bath under identical conditions. The following Table compares the uniformities, as deduced from sheet resistance measurements, of the three wafers after the deposition of a copper layer having a nominal thickness of 1.5 microns.

TABLE 1Non-uniformityEnhancementStandard devi...

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Abstract

This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 09 / 885,232 filed on Jun. 20, 2001 now U.S. Pat. No. 6,811,675. Application Ser. No. 09 / 885,232 is a Continuation of U.S. application Ser. No. 09 / 387,033 filed on Aug. 31, 1999, now U.S. Pat. No. 6,290,833. Application Ser. No. 09 / 387,033 is a Continuation of application International Application No. PCT / US99 / 06306 filed on Mar. 22, 1999. PCT / US99 / 06306 is a continuation-in-part of U.S. application Ser. No. 09 / 045,245, filed on Mar. 20, 1998, and claims the benefit of U.S. Provisional Application No. 60 / 085,675 filed on May 15, 1998.BACKGROUND OF THE INVENTION [0002] In the fabrication of microelectronic devices, application of one or more metallization layers is often an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, such as read / write heads, but is more often used to interconnect com...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C23C28/00C23C28/02C25D3/38C25D5/10C25D7/12H01L21/288H01L21/445H01L21/768H05K3/42
CPCC23C28/322C23C28/34C25D3/38C25D5/10H01L21/2885C25D7/123H01L21/76868H01L21/76873H01L21/76877H01L2221/1089H05K3/423H01L21/76843C25D5/627H01L21/20
Inventor CHEN, LINLIN
Owner SEMITOOL INC
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