Stacking system and method

Abstract

The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

Description

RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10 / 400,309 filed Mar. 27, 2003, which is a continuation of U.S. application Ser. No. 10 / 005,581, filed Oct. 26, 2001, now issued as U.S. Pat. No. 6,576,992, each of which is hereby incorporated by reference for all purposes.TECHNICAL FIELD [0002] The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages. BACKGROUND OF THE INVENTION [0003] A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect ...

AI Technical Summary

Benefits of technology

[0017] In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with a pair of flex circuits. Each of the pair of flex circuits is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB).

Problems solved by technology

Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages.

Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.

Such techniques provide alternatives, but require topologies of added cost and complexity.

The previous known methods for stacking CSPs apparently have various deficiencies including complex structural arrangements and thermal or high frequency performance issues.

During such reliability evaluations, CSP devices often exhibit temperature cycle performance issues.

The issues associated with temp cycle performance in single CSPs will likely arise in those prior art CSP stacking solutions where the stack is offset from the PWB or application platform by only the height of the lower CSP ball grid array.

Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.

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