Voltage controlled delay loop and method with injection point control

Abstract

A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present invention is related to U.S. patent application Ser. No. ______, entitled “Voltage Controlled Delay Loop with Central Interpolator,” filed contemporaneously herewith and incorporated by reference herein.FIELD OF THE INVENTION [0002] The present invention is related to techniques for clock and data recovery (CDR) and, more particularly, to methods and apparatus for digital control of the generation and selection of different phases of a clock signal. BACKGROUND OF THE INVENTION [0003] In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock sig...

AI Technical Summary

Benefits of technology

[0007] The injection point control of the present invention allows a desired phase relationship to be maintained between the reference clock and a sample clock. The granularity of the disclosed voltage controlled delay loop is equal to the delay associated with each delay element.

Problems solved by technology

While such voltage controlled delay loops effectively generate the sampling clocks and control the delay stages to maintain alignment of the reference clock signal and the last timing signal, they suffer from a number of limitations, which if overcome, could further improve the utility of such voltage controlled delay loops.

For example, the analog implementation of the phase lock controller is complex and generally cannot be easily ported from one technology to another.

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