Apparatus and method for adjusting clock skew

Abstract

The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers there is no reduction in skew between the two internal signals. In a preferred embodiment, the invention provides back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in misread data signals.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to integrated circuit chips and, in particular, to differential input buffers capable of reducing clock signal skew. [0003] 2. Description of the Related Art [0004] Internal circuit functions in synchronous integrated circuits, e.g. SDRAM chips, are performed in response to transitions of an internal clock signal. Clock signals are signals that vary between a low voltage and a high voltage at regular intervals and are referenced to a fixed voltage, typically either the low voltage or the high voltage. The internal clock signal is derived from an external clock signal that has been passed through an input buffer as it enters the integrated circuit. The input buffer detects transitions in the external clock signal and outputs an internal clock signal, usually at a different reference voltage than the external clock signal. [0005] Some circuits require differential input clock signals at a pair o...

AI Technical Summary

Benefits of technology

"The present invention provides a circuit that can generate inverse clock signals with reduced skew using the same input buffer as the address and data signals on an integrated circuit. This is achieved by using back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states, and the faster internal clock signal has an extra inverter fighting it when it switches states. This reduces the skew of the two signals, allowing for faster operation of the integrated circuit and a reduction in error in downstream circuits using the two signals."

Problems solved by technology

However, when a buffer circuit produces complimentary output signals, the output signals are susceptible to skew.

If the two clock signals are skewed, e.g. they are out of phase with one another, then the first data signal may arrive too early or too late to be sampled by the second data signal.

Race conditions can cause an incorrect data value to be read when a data signal is sampled since the first data signal is not present when it is to be sampled.

Therefore, race conditions can cause an integrated circuit to malfunction.

Such skew times are unacceptable for some applications, such as very low jitter delay locked loops and phase-locked loops.

In such circuits, skewed input signals can cause instability, drift and jitter in the output signals.

While such a circuit buffers the external clock signals, it does not eliminate any pre-existing skew between the external clock signals.

In addition, though it is useful for the regulated portion of an integrated circuit the resulting internal clock signals do not track well with the address and data inputs across the circuits operating voltage.

Due to the large number and interdependence of transistors, the gate loading for this circuit leads to crossing point accuracy problems in response to fluctuations in voltage and temperature conditions.

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