Technique for accommodating electronic components on a multilayer signal routing device

Abstract

A technique for accommodating electronic components on a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a multilayer signal routing device comprising a primary surface and a secondary surface. The primary surface may have a plurality of electrically conductive pads formed thereon, wherein a group of the plurality of electrically conductive pads is in respective electrical connection with a group of electrically conductive micro-vias formed in the multilayer signal routing device. The secondary surface may have a channel formed thereon coinciding with the location of the group of electrically conductive micro-vias, wherein the channel has a channel area on the secondary surface for accommodating an electronic component mounted on the secondary surface.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This patent application is a divisional of U.S. patent application Ser. No. 10 / 716,599, filed Nov. 20, 2003, which claims priority to U.S. Provisional Patent Application No. 60 / 427,865, filed Nov. 20, 2002, each of which is hereby incorporated by reference herein in its entirety. [0002] The above-referenced U.S. patent application Ser. No. 10 / 716,599 is a continuation-in-part of U.S. patent application Ser. No. 10 / 101,211, filed Mar. 20, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09 / 651,188, filed Aug. 30, 2000, now U.S. Pat. No. 6,388,890, which claims priority to U.S. Provisional Patent Application No. 60 / 212,387, filed Jun. 19, 2000, each of which is hereby incorporated by reference herein in its entirety. [0003] The above-referenced U.S. patent application Ser. No. 10 / 716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10 / 326,123, filed Dec. 23, 2002, now U.S. Pat. No. 7,069,650,...

AI Technical Summary

Benefits of technology

This approach enhances signal integrity by placing additional components near signal driver contacts, reducing parasitic effects and increasing component density, while also simplifying the manufacturing process and reducing costs.

Problems solved by technology

These single routing layer circuit boards have severe limitations with regard to the number of electrical signals that can be routed between electronic components mounted on the same circuit board.

That is, the number of electrical signals that can be routed between electronic components mounted on a single routing layer circuit board is limited by the amount of area on the single routing layer.

The area limitations associated with single routing layer circuit boards led to the development of multilayer PCBs.

While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, reliability and other problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components.

While electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough.

That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance, which can adversely affect signals propagating along each electrically conductive via.

In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof.

Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via.

These adverse affects only increase as the number of layers in a multilayer PCB increase.

However, this if often difficult to achieve since the signal driver contact may be located within the interior of a contact array of the electronic component, and thus there is no place to mount the resistive, capacitive, and / or inductive components.

However, the cost and maturity of suitable technologies for this proposed solution make it impractical.

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