Semiconductor device having a multilayer interconnection structure and fabrication process thereof
a technology of interconnection structure and semiconductor device, which is applied in the direction of semiconductor device, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of serious deformation of yield and reliability of semiconductor device, deterioration of resistance to electromigration or stress migration, etc., to achieve effective suppression of defects in contact structure, effective suppression of problem of corrosion of copper interconnection pattern, effect of improving throughput of forming multi-layer interconnection structur
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first embodiment
[0071]FIG. 4 is a diagram showing a multilayer interconnection structure according to a first embodiment of the present invention.
[0072] Referring to FIG. 4, a wiring groove 21G is formed in an interlayer insulation film 21, and the wiring groove 21G is covered by a barrier metal film 21A. Further, the wiring groove is formed with a copper interconnection pattern 21Cu by using a damascene process. Here, it should be noted that the interlayer insulation film 21 is formed on the silicon substrate not illustrated, and an interlayer insulation film 22 is formed on the interlayer insulation film 21 via a SiN barrier film 22N. Further, a via-hole 22V exposing the copper interconnection pattern 21Cu is formed in the interlayer insulation film 22 so as to penetrate through the barrier film 22N with an aspect ratio of 1.25 or more, such as 2.4.
[0073] In one example, the interlayer insulation film is formed by polishing an SiO2 film, formed by a plasma CVD process with the thickness of 1100...
second embodiment
[0099]FIG. 9 shows the process pressure sequence used with the deposition process of the W film 22W in FIG. 5D explained before. Further, FIGS. 10A and 10B show a detailed process flow of the process of FIG. 5D corresponding to the sequence of FIG. 9.
[0100] The inventor of the present invention has discovered, in the investigation that constitutes the foundation of the present invention, that occurrence of defect in the barrier metal film 22A or copper interconnection pattern 21Cu at the time of deposition of the tungsten film is successfully suppressed when the film formation process of the tungsten film 22W of FIG. 5D is conducted while supplying a hydrogen gas.
[0101] Referring to FIG. 9, the structure of FIG. 5C is first heated in the present embodiment to a predetermined temperature in the ambient containing hydrogen (Stage 1), and a tungsten nucleation layer (passivation film) 23W1 is formed on a TiN under layer 22B of FIG. 5C as shown in FIG. 10A by an ALD (atomic layer depo...
third embodiment
[0122]FIG. 15 shows the method of forming a multilayer interconnection structure according to a third embodiment of the present invention that uses a cluster type substrate processing apparatus 200.
[0123] Referring to FIG. 15, the cluster-type substrate processing apparatus 200 includes a vacuum transportation chamber 201 to which a load-lock chamber 200A, a sputtering chamber 200B, which in turn accommodates therein a reactive sputtering apparatus 100 equipped with a Ta target 104 and conducting deposition of TaN as explained previously with reference to FIG. 6, a sputtering chamber 200C, which in turn accommodates therein a reactive sputtering apparatus conducting deposition of the TiN film, and a CVD chamber 200D for conducting deposition of the tungsten film 23W1 or 23W are connected.
[0124] Thus, the substrate of the state of FIG. 5A is introduced into the load-lock chamber 200A, and deposition of the TaN film 22A is conducted by the recipe explained previously with reference ...
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