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Data processing apparatus

a data processing apparatus and data processing technology, applied in the direction of instruments, specific program execution arrangements, program control, etc., can solve the problems of unsatisfactory increase in achieve the effect of improving the throughput of the data processing apparatus, maximizing throughput, and increasing the amount of resources required

Active Publication Date: 2007-05-10
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0018] The present invention also recognises that whilst it would be possible to maximise throughput by, for example, increasing the number of registers which feed the permute logic, increasing the number of registers which receive the permuted data elements from the permute logic or by duplicating the permute logic or the registers used to buffer the data elements to be permuted, such an approach undesirably increases the amount of resources required.
[0041] Accordingly, the permute logic takes advantage of the fact that the size of the bubble created within the pipeline stages will match the number of permuted data elements required to be provided from the permute logic, thereby filling the bubble.

Problems solved by technology

The present invention also recognises that whilst it would be possible to maximise throughput by, for example, increasing the number of registers which feed the permute logic, increasing the number of registers which receive the permuted data elements from the permute logic or by duplicating the permute logic or the registers used to buffer the data elements to be permuted, such an approach undesirably increases the amount of resources required.

Method used

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first embodiment

[0051]FIG. 3A illustrates a data processing apparatus, generally 50, including forwarding logic and permute logic according to the present invention. The data processing apparatus 50 has a plurality of pipelined stages.

[0052] The pipeline stages include a fetch stage and four execute stages. In overview, data elements provided to the permute logic 12 from the register R1 are distributed across the registers A to D. Whilst the data elements are being distributed across the registers A to D by the permute logic 12, a bubble is created in the subsequent pipelined stages. Accordingly, forwarding logic in the form of multiplexers 14, 16 and 18, together with the paths 13, 15, 17 and 19 are provided which enable data elements from the registers A to D to be forwarded to the subsequent pipelined stages in order to fill the bubble. Accordingly, as will be explained in more detail below, this arrangement enables data elements to be provided in each clock cycle to the permute logic 12 and per...

second embodiment

[0089]FIG. 4 illustrates a data processing apparatus, generally 50′, including forwarding logic and permute logic according to the present invention. The data processing apparatus 50′ has a plurality of pipelined stages.

[0090] The pipeline stages include a fetch stage, four execute stages and a write-back stage. In overview, data elements provided to the permute logic 12 from the register R1 are distributed across the registers A to D. Whilst the data elements are being distributed across the registers A to D by the permute logic 12, a bubble is created in the subsequent pipelined stages. Accordingly, forwarding logic in the form of multiplexers 14, 20, 22 and 24, together with the paths 21, 23, 25, 27, 29, 31 and 33 are provided which enable data elements from the registers A to D to be forwarded to the subsequent pipelined stages in order to fill the bubble. Accordingly, this arrangement enables data elements to be provided in each clock cycle to the permute logic 12 and permuted ...

third embodiment

[0091]FIG. 5 illustrates a data processing apparatus, generally 50″, according to the present invention. In this arrangement, data -elements flow into the fetch and neon execute 1 to 3 stages. These data elements are then forwarded to the neon execute 4 stage which contains the permute logic. Forwarding the data in this way will create a bubble in the pipeline which can then be filled at the neon execute stage with groups of permuted data elements.

[0092] Hence, the bubble created in the fetch, neon execute 1 and neon execute 2 stages when forwarding the data elements stored therein is filled at the neon execute 4 stage with permuted groups of data elements. In this way, the delay between processing back to back permute instructions is reduced. Also, the performance throughput of the pipeline is maximised since data elements can be constantly provided to the neon execute 1 stage and constantly output by the neon execute 4 stage.

[0093] Accordingly, the performance limitation which wo...

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Abstract

Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages. By forwarding the data elements to fill the bubble an improved throughput can be achieved and since a constant stream of data can be transformed without the need to increase the number of input or output registers required to support the permute logic, the need to duplicate the permute logic or the need to introduce any additional storage elements.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a data processing apparatus and method. Embodiments of the present invention relate to a data processing apparatus and method operable to perform permute operations. [0003] 2. Description of the Prior Art [0004] Permute operations are known. Permute operations typically take a sequence of data elements and reorder or permutate the data elements to create a new sequence. [0005] For example, as shown in FIG. 1, a sequence of consecutive data elements 0 to 15 are provided. A permute unit 10 is provided which performs a permute operation on the data elements in response to a permute instruction. Such an instruction is typically supported by a vector or single instruction multiple data (SIMD) data processing apparatus for supporting transformation between arrays of structures (AoS) and structures of arrays (AoS). UK patent application 2,409,063 filed on 9 Dec. 2003 by ARM Limited describe...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F15/00
CPCG06F9/3836G06F9/3855G06F9/3856
Inventor BELNET, LIONELBROCHIER, STEPHANE ERIC SEBASTIENFORD, SIMON ANDREW
Owner ARM LTD
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