Semiconductor device and a method of manufacturing the same

Abstract

A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p− type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p− type semiconductor region is formed under a n+ type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Continuation application of U.S. application Ser. No. 10 / 886,041 filed on Jul. 8, 2004. Priority is claimed based on U.S. application Ser. No. 10 / 886,041 filed on Jul. 8, 2004, which claims priority to Japanese Patent Application No. 2003-286142 filed on Aug. 4, 2003, all of which is incorporated by reference.FIELD OF THE INVENTION [0002] The invention relates to a semiconductor device and for a method of manufacturing the same, and in particular, to a semiconductor device and method employing power MISFETs (Metal Insulator Semiconductor Field Effect Transistors). BACKGROUND OF THE INVENTION [0003] In the case of a trench (groove) gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a structure incorporating, for example, a p-type epitaxial layer as an upper layer of an n+ type substrate, it is known to reduce the risk of punch-through breakdown of the trench gate by forming an n-type...

AI Technical Summary

Benefits of technology

"The patent text discusses a power MISFET used in a DC-DC converter and the need to reduce capacitance for better performance. The technical effect of the patent is to reduce the input and feedback capacitance of the power MISFET to minimize switching loss and drive loss in the converter. This is achieved by narrowing the grooves in which the gate is formed and reducing the distance between the gate and the source and drain regions. This reduces the input capacitance and the feedback capacitance, which helps to improve the performance of the DC-DC converter."

Problems solved by technology

Accordingly, there is a trend for a DC-DC converter towards higher frequency, and as the DC-DC converter operates higher in frequency, an increase in switching loss and drive loss may occur in a power MISFET.

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