Method for forming a copper metal interconnection of a semiconductor device

Abstract

Embodiments relate to a method for forming a copper metal interconnection of a semiconductor device. In embodiments, a copper metal interconnection may be formed through a damascene process. The method may include forming a first copper plating layer on an interlayer dielectric layer of the semiconductor substrate by performing an electrical-chemical plating scheme with a first plating distance, measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance according to the surface uniformity of the first copper plating layer.

Description

[0001] The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0134077 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety. BACKGROUND [0002] Semiconductor manufacturing processes may be classified into a front end of the line (FEOL) process, which may be used to form a transistor on a silicon substrate, and a back end of the line (BEOL) process, which may be used to form metal interconnections. The BEOL process may refer to a process of forming power supply and signal transfer paths on a silicon substrate to connect transistors to each other to constitute an integrated circuit. [0003] Copper (Cu), which is a material that may have high EM (Electro-migration) tolerance, may be used for such a BEOL process. However, since copper may not be easily etched, and may be oxidized during an interconnection process, it may be difficult to pattern copper using a typical photo process technology. [00...

AI Technical Summary

Benefits of technology

[0022] Embodiments relate to a method for forming a copper metal interconnection through a damascene process that may be capable of minimizing the creation of copper residue.

Problems solved by technology

However, since copper may not be easily etched, and may be oxidized during an interconnection process, it may be difficult to pattern copper using a typical photo process technology.

When manufacturing a copper metal interconnection using the damascene process, defects may occur due to copper residue after the CMP process.

Since such copper residue 42 may disconnect the patterns from each other, the copper residue may be a factor that reduce a performance and yield rate of a semiconductor device.

In particular, copper residue may be generated due to non-uniformity of a copper plating layer formed through a copper ECP process.

In addition, during the copper ECP process, since bubbles may accumulate in a plating solution, an unexpected current may be induced into the wafer.

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