Low inductance high ESR capacitor

Abstract

A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of U.S. patent Ser. No. 11 / 334,271, filed Jan. 18, 2006 (attorney docket number 31433 / 142) which is now pending and incorporated by reference.BACKGROUND[0002]The present invention is related to a low inductance capacitor having two terminals. More particularly, the present invention is related to a low inductance multi-layer capacitor having two terminals which electrically connect to the lead-out tabs of interleaved T shaped electrodes.[0003]In summary, the art has been seeking a low inductance multi-layer capacitor for use in high frequency decoupling applications which is effective and inexpensive to manufacture, as well as simple to use. Recent developments in microprocessors and memory technologies have led to an increased demand for faster switching speeds and greater densities in integrated circuits. Because of these demands, higher operating frequencies or switching speeds are required wh...

AI Technical Summary

Benefits of technology

The present invention provides a capacitor that has low mutual inductance, low parasitic inductance, increased effective equivalent series resistance (ESR), and inherently lower equivalent series inductance (ESL) and can be used in high frequency decoupling applications. The capacitor has simple manufacturing processes and easy mounting capabilities. The capacitor has first and second internal electrode plates arranged parallel to each other with dielectric there between. The first and second external electrode terminals are on a common surface of the capacitor. The capacitor also has more than one interleaved internal electrode plate where each plate has first and second lead-out tabs, a land, and a planar element. Both external electrode terminals are on a common surface of the capacitor.

Problems solved by technology

Because of these demands, higher operating frequencies or switching speeds are required which cause larger current fluctuations and difficulties in controlling voltage fluctuations accompanying these larger current fluctuations.

The use of larger value capacitors, however, creates two problems.

First, there is an ongoing demand for smaller and smaller devices due to the ongoing desire for the miniaturization of electronic apparatuses.

Second, the larger the capacitor size, the larger the parasitic inductance becomes.

Parasitic inductance is almost always undesirable because it degrades the effectiveness of the capacitor.

Capacitors with large parasitic inductances have relatively low resonance frequency combined with relatively high impedance at high frequencies making them unusable for many high-speed applications.

Mutual inductance is also undesirable in an electric circuit because it causes unwanted coupling between conductors in a circuit.

While the '300 patent discloses a capacitor with lower parasitic inductance than standard multilayer capacitors, it does not disclose a capacitor with lower mutual inductance.

Furthermore, the '300 patent still maintains a high parasitic inductance due to the limiting surface area of the terminations.

The capacitors disclosed in the '300 patent are expensive to manufacture and have limiting mounting capabilities due to the use of separate external contact bar terminations.

Further, the '355 patent requires the use of solder stops and maintains limiting mounting capabilities.

The serpentine pattern disclosed in the '136 patent does not effectively reduce ESR because each electrode plate has a wide surface area when the current enters each electrode plate from the termination.

These patents do not disclose capacitors with low mutual inductance and provide for capacitors with high parasitic inductance due to the limiting surface area of the interdigitated external terminations.

Moreover, the items described in these patents are expensive to manufacture because of the lack of symmetry of the internal electrodes and the limiting mounting capabilities due to the use of separate external contact bar terminations.

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