Method and apparatus for plasma processing

Abstract

The invention provides a plasma processing apparatus capable of minimizing the non-uniformity of potential distribution around wafer circumference, and providing a uniform process across the wafer surface. The apparatus is equipped with a focus ring formed of a dielectric, a conductor or a semiconductor and having RF applied thereto, the design of which is optimized for processing based on a design technique clarifying physical conditions for flattening a sheath-plasma interface above a wafer and the sheath-plasma interface above the focus ring. A surface voltage of the focus ring is determined to be not less than a minimum voltage for preventing reaction products caused by wafer processing from depositing thereon. The surface height, surface voltage, material and structure of the focus ring are optimized so that the height of an ion sheath formed on the focus ring surface is either equal or has a height difference within an appropriate tolerance range to the height of the ion sheath formed on the wafer surface. Optimization of the structure is realized by setting up an appropriate tolerance range taking into consideration the variation caused by consumption of the focus ring.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Divisional application of application Ser. No. 10 / 902,032, filed Jul. 30, 2004, which claims priority from Japanese patent application No. JP 2004-118513, filed on Apr. 14, 2004, the contents of which are incorporated herein by reference in their entirety.FIELD OF THE INVENTION [0002] The present invention relates to the art of semiconductor fabrication. Especially, the invention relates to a structure of a wafer stage that affects the etching contour when providing an etching process to a semiconductor wafer using plasma. DESCRIPTION OF THE RELATED ART [0003] Recently, along with the enhancement in the integration of semiconductor elements, the circuit patterns have become more and more refined, and the demanded accuracy of processing dimension has become stricter. Further, the wafer diameter is increased to 300 mm in the attempt to reduce fabrication costs of the semiconductor elements, but processing is required ...

AI Technical Summary

Benefits of technology

The solution ensures uniform processing across the wafer surface, maximizes etch rate uniformity, and extends the focus ring's life by optimizing its structure to maintain uniformity and prevent deposition, thereby reducing fabrication costs and improving yield.

Problems solved by technology

However, a ceramic cover for protecting an electrostatic chuck is disposed near the outer circumference of the wafer, for example, which causes non-uniformity of the electric field at the circumference compared to the center of the wafer, and causes the drawback of non-uniformity of the wafer process.

These are serious problems since they cause the increase of fabrication costs

According to the above-mentioned prior art methods, however, there is no disclosure of a technique for optimizing the focus ring structure.

However, the prior art lacks to disclose such technique.

Therefore, the electric field correcting function of the focus ring changes with time and deteriorated.

Therefore, it is necessary to set up a tolerance and to optimize the structure accordingly, but the prior art lacks to disclose such technique.

The deposits on the focus ring surface may become particles that adhere to the wafer and cause defective products to be fabricated.

This may cause time variation of the wafer process according to which the result of wafer processing is changed with time from the starting of wafer processing.

The conventional methods lack to provide a method for coping with the deposition, so the focus ring may be helpful to uniformize the processing, but it is not actually useful if deposition occurs.

Of course, patent document 5 lacks to disclose any teachings related to determining the tolerance and optimizing the structure based thereon.

The drawback of the conventional optimization process disclosed in document 5 is that there is no teaching of a physical method or design technique for flattening the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring.

The optimization of the structure is impossible to carry out without a physical mechanism or a design technique.

Even when an appropriate structure is discovered through experimental methods, it is difficult to prove experimentally that the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring are flat, and the flatness cannot be ensured.

The drawback of the technique disclosed in patent document 6 mentioned above is that the generation of a uniform sheath voltage realized by equalizing the impedance between the lower electrode and plasma at the wafer portion and at the focus ring portion does not guarantee the flattening of the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring.

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