High-performance RISC-DSP

Abstract

A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seamless transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low overhead interrupts.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 09 / 637,500, filed Aug. 11, 2000, which is incorporated herein by reference in its entirety, and which claims the benefit of U.S. Provisional Application No. 60 / 148,652, filed Aug. 13, 1999.FIELD OF THE INVENTION [0002] The present invention relates to digital signal processor (DSP) architectures. BACKGROUND OF THE INVENTION [0003] With the increasing commercial importance of DSP-intensive applications, such as wireless communication, modems, and computer telephony, has come an increasing recognition of the benefit of implementing DSP functions on a CPU. Not only are CPUs usually needed for memory management, user interface and Internet Protocol software, CPUs also have excellent third-party software tool support. [0004] Implementing certain DSP algorithms, such as the FIR Filter or Discrete Cosine Transform (DC7), in software, however, may degrade performance up to a...

AI Technical Summary

Benefits of technology

"The present invention provides systems and methods for a more efficient implementation of digital signal processing algorithms and the use of CPU resources. This is achieved through a configuration that allows for the use of two execution pipelines capable of executing RISC instructions, instruction fetch logic that simultaneously fetches two instructions, and control logic that allows the pipelines to operate independently. Additionally, the invention includes a memory that stores instructions having opcodes, an instruction decoder that identifies a relocatable opcode to designate subopcodes, and a subopcode detector that decodes subopcodes if the instruction decoder identifies the relocatable opcode. Furthermore, the invention includes a register pair and means for executing a multiply instruction on a number stored in the register pair, including first means for performing multiply instructions on higher-order portions of each register, second means for performing multiply instructions on the remaining portions of each register, and third means for combining the results from the first and second means. Finally, the invention includes a circular buffer control circuit that includes means for comparing a pointer to an address in a selected one of the circular buffer end registers, and means for restoring the address in the one of the circular buffer start registers associated with the selected circular buffer end register if the pointer matches the address in the selected circular buffer end register."

Problems solved by technology

Implementing certain DSP algorithms, such as the FIR Filter or Discrete Cosine Transform (DC7), in software, however, may degrade performance up to an order of magnitude as compared to specialized DSPs.

Another difficulty is the problem of deterministic real-time allocation in sophisticated CPUs.

These approaches, however, impose a substantial burden on the CPU in managing DSP functions.

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