Semiconductor device and method of manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

Description

RELATED APPLICATION DATA[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 366,123, filed Mar. 2, 2006, the entirety of which is incorporated herein by reference to the extent permitted by law. The present invention claims priority to Japanese Patent Application No. 2005-075165 filed in the Japanese Patent Office on Mar. 16, 2005, the entirety of which also is incorporated by reference herein to the extent permitted by law.BACKGROUND OF THE INVENTION[0002]The present invention relates to semiconductor devices referred to as a so-called system in package, in which a plurality of semiconductor chips are mounted in one package form, and manufacturing methods thereof. The invention relates more particularly to a semiconductor device having a structure in which a semiconductor substrate is used to electrically coupling a plurality of semiconductor chips, and a manufacturing method thereof.[0003]Recent trends of electronic apparatuses toward higher functions are...

AI Technical Summary

Benefits of technology

[0009]The SiP approach of the Patent Document 1 however requires the formation of the through vias penetrating the silicon interposer substrate 53 and the formation of the conductive portions 56 buried in the through vias. Silicon etching for forming the through vias and the precipitation of the conductive portions 56 by plating in the through vias take high costs and long time periods, which problematically results in an increase of manufacturing costs of the entire semiconductor device.

Problems solved by technology

Silicon etching for forming the through vias and the precipitation of the conductive portions 56 by plating in the through vias take high costs and long time periods, which problematically results in an increase of manufacturing costs of the entire semiconductor device.

Due to this large pitch of the pads 49, the size of the silicon interposer substrate 53 in the plane direction thereof tends to be large, which also leads to high costs.

The existence of these lead-to-external interconnections reduces the flexibility of route layout of the chip-to-chip interconnections, and thus the length of the chip-to-chip interconnections tends to be large, which readily causes delay of signal transmission between the semiconductor chips 62a and 62b.

Images