Reduced Frequency Data Processing Using a Matched Filter Set Front End

Abstract

Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention is related to systems and methods for processing information, and more particularly to systems and methods for processing a series of encoded bits.

[0002] Data transfer systems typically include a receiver that converts an analog input into a stream of digital bits representing the analog input. For example, in a hard disk drive system, digital information is converted to an analog signal that is stored as a magnetic signal on a storage medium. The magnetic information is sensed and converted to an analog signal. The received analog signal is converted back to digital information representing the digital information originally provided to the storage medium. As another example, a wireless communication system involves a transmitter that receives digital information, and converts it to an analog signal that is transmitted. The analog signal is received and converted back to the original digital information that was originally prepa...

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