Double-triggered logic circuit

Abstract

A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss.

Description

FIELD OF THE INVENTION[0001]The present invention relates to a composite logic circuit and particularly to a double-triggered logic circuit.BACKGROUND OF THE INVENTION[0002]Nowadays, digital systems are increasingly diversified. How to reduce power consumption of chipsets is a one of main research focuses. Digital synchronous systems usually have one or more sets of clock systems. Clock signals are used to control data movement. The clock system consists of a clock system distribution network and a flip-flop. It consumes greatest power in the chipset. Power consumption can be divided into static power consumption and dynamic power consumption. The dynamic power consumption can be divided into switch power consumption and short circuit current power consumption. The static power consumption mostly is leakage power consumption.[0003]The technique for reducing power can target reducing static power and reducing dynamic power. As the dynamic power consumption always is much greater than...

AI Technical Summary

Benefits of technology

"The present invention provides a double-triggered logic circuit that consists of two types of logic circuits and is structured at a lower complexity. The circuit includes a smaller number of transistors, reducing complexity and power consumption. It also eliminates the need for a path of grounding power supply, reducing short circuit current and power consumption. The circuit includes a MUX circuit that can be omitted, further reducing time delay and power-delay-product. The technical effects of the invention include reduced complexity, lower power consumption, and improved performance."

Problems solved by technology

It consumes greatest power in the chipset.

The static power consumption mostly is leakage power consumption.

But lowering the voltage often results in lower speeds.

Such a phenomenon creates a race trough problem.

But the transmission delay is longer.

However, in a serial-and-parallel environment a greater loading capacitance occurs that could result in not able to generate the pulses.

As a result, the explicit-pulsed-triggered flip-flop does not provide as much benefits as the implicit-pulsed-trigger flip-flop does.

Moreover, with addition of the pulse generator on the circuit, power consumption increases.

Although the circuit is simpler, the loading capacitance of the clock signal input (CLK) 9D is greater and huge power consumption is caused.

On CMOS circuits of the conventional logic circuits, such as those for applications of XOR, XNOR, AND, OR and MUX, the circuits are relatively simple, but they have the problem of threshold voltage loss.

The problem of threshold voltage loss is because circuits cannot function at a low voltage and consume a greater amount of power.

Such a problem creates other problems on the circuits such as not adequate driving power and short circuit current.

In short, adopted the conventional techniques to make a customized circuit are time-consuming and take great efforts.

It requires a lot of time to design, execute, customize features and perform integration.

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