Design apparatus of semiconductor device, design method of semiconductor device, and semiconductor device

Abstract

A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application claims the benefit of patent application numbers 2011-023313 filed in Japan on Feb. 4, 2011 and 2010-172600 filed in Japan on Jul. 30, 2010, the subject matters of which are hereby incorporated herein by reference.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to a design apparatus of a semiconductor device, a design method of a semiconductor device, and a semiconductor device, and more particularly, relates to a design apparatus of a semiconductor device, a design method of a semiconductor device, and a semiconductor device, each of which improves reliability of a wiring line.[0004]2. Description of Related Art[0005]In a wiring line of a semiconductor device, it is known that the electromigration (hereinafter referred to as EM) sometimes occurs. Recently, in the semiconductor device, since a size of the wiring line is reduced, deterioration of reliability due to the EM has been concer...

AI Technical Summary

Benefits of technology

[0021]According to the present invention, problems such as increasing of a circuit area, lengthening of a design time, and a difficulty of correction in a case of a large-scale circuit are not caused, and thus a wiring line where occurrence of the EM is significantly suppressed can be designed.

Problems solved by technology

Recently, in the semiconductor device, since a size of the wiring line is reduced, deterioration of reliability due to the EM has been concerned.

At first, a wiring line of a test structure having a layout in a worst case as a most disadvantageous case of the reliability is prepared.

Correction of the configuration of a wiring line such as extension of a wiring width and increasing of the number of wiring lines has problems: that an area of the circuit becomes large; that a design time is lengthened by repeating correction and confirmation; that the configuration is hard to be corrected in a large-scale circuit when balancing with other parts should be considered; and the like.

Images