Structure and method for nfet with high k metal gate

Abstract

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.

Description

BACKGROUND[0001]Field effect transistors (FETs) have been used in conventional integrated circuit (IC) design. Due to shrinking technology nodes, high-k dielectric material and metal are often considered to form a gate stack for a FET. Integration issues exist when forming various metal-gate FETs onto a single IC chip, especially when resistors are integrated in an IC circuit. One issue is related with dishing effect during a polishing process. In another example, a gate replacement process includes an etch process to remove the polysilicon gate. However, the formed polysilicon resistors can be damaged and recessed by the etch process, causing the deviation of the resistance of the polysilicon resistor from the designed target. Therefore, a structure integrated with high k metal gate a method making the same are needed to address the above issues.BRIEF DESCRIPTION OF THE DRAWINGS[0002]Aspects of the present disclosure are best understood from the following detailed description when ...

AI Technical Summary

Benefits of technology

The patent text describes a method and structure for making a semiconductor device with a metal gate stack and a polysilicon resistor. The technical effects of the patent include addressing issues with dishing and etching processes when integrating various features onto a single chip. The method includes providing a semiconductor substrate with various doped features and isolation features, such as STI, and then sequentially adding layers to form the metal gate stack and the polysilicon resistor. The structure includes various devices and polysilicon resistors integrated on the semiconductor substrate. The technical effects of the patent include improved performance and reliability of the semiconductor device and more efficient fabrication processes.

Problems solved by technology

Integration issues exist when forming various metal-gate FETs onto a single IC chip, especially when resistors are integrated in an IC circuit.

One issue is related with dishing effect during a polishing process.

However, the formed polysilicon resistors can be damaged and recessed by the etch process, causing the deviation of the resistance of the polysilicon resistor from the designed target.

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