Stacked memory device with metadata mangement

Abstract

A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is related to U.S. patent application Ser. No. ______ (Docket No. 1458-110245), filed on even date herewith and entitled “Stacked Memory Device with Helper Processor,” the entirety of which is incorporated by reference herein.BACKGROUND[0002]1. Field of the Disclosure[0003]The present disclosure generally relates to memory devices, and more particularly, to stacked memory devices.[0004]2. Description of the Related Art[0005]Memory bandwidth and latency are significant performance bottlenecks in many processing systems. These performance factors may be improved to a degree through the use of stacked, or three-dimensional (3D), memory, which provides increased bandwidth and reduced intra-device latency through the use of through-silicon vias (TSVs) to interconnect multiple stacked layers of memory. However, system memory and other large-scale memory typically are implemented as separate from the other components of t...

AI Technical Summary

Problems solved by technology

Memory bandwidth and latency are significant performance bottlenecks in many processing systems.

A system implementing 3D stacked memory therefore can continue to be bandwidth-limited due to the bandwidth of the interconnect connecting the 3D stacked memory to the other components and latency-limited due to the propagation delay of the signaling traversing the relatively-long interconnect and the handshaking process needed to conduct such signaling.

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