Channel-Last Methods for Making FETS

Abstract

Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority from U.S. Provisional Patent Application No. 61 / 779,740, filed Mar. 13, 2013 which is incorporated herein by reference in its entirety for all purposes.FIELD OF THE INVENTION[0002]One or more embodiments of the present invention relate to field effect transistors and methods of making field effect transistors.BACKGROUND[0003]As feature sizes for semiconductor devices continue to get smaller and smaller, manufacturers are increasingly building devices entirely on top of substrate materials so that all device components are explicitly fabricated and controlled for size and functional characteristics. The semiconductor material used for the device components may be different from that of the substrate. For example, a high-speed field effect transistor (FET) can be made using a doped Ge semiconductor deposited on a Si wafer. The Si wafer does not provide any device function beyond being a substrate support. All...

AI Technical Summary

Benefits of technology

The patent text describes a method for making a field-effect transistor (FET) with improved performance. The method involves using a specific process to form layers of the FET, including a substrate, a first layer, a second layer, a third layer, and a fourth layer. The third layer is made of a high-κ dielectric material and is in ohmic contact with the source and drain electrodes. The fourth layer is made of conductive materials and acts as the source and drain electrodes. The method also includes the use of a fifth layer as an interface layer and a sixth layer as a passivation layer. The use of these specific layers and methods of formation results in improved performance of the FET, including reduced current leakage, better current flow, and reduced power consumption.

Problems solved by technology

The Si wafer does not provide any device function beyond being a substrate support.

Many problems arise in fabricating working devices using the gate stack of FIG. 1.

The GeOx, layer tends to be unstable.

It is difficult to devise a process where device parameters can be independently controlled during fabrication.

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