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Tapered fin field effect transistor

a technology of field effect transistor and fin, which is applied in the direction of basic electric elements, semiconductor devices, electrical equipment, etc., can solve the problems of gate dielectric scaling, increasing difficulty in controlling the channel through conventional means such as doping profile control, and achieve the effect of reducing the lateral width of the bottom portion, enhancing the electrostatic control of the channel, and reducing the thickness of the etch residue material

Inactive Publication Date: 2014-10-16
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a way to improve the control of a transistor by using a tapered fin design. A layer of semiconductor and dielectric material is formed on an insulator layer, and the semiconductor material is shaped like a tapering effect. An etch process is used to remove a layer of material from the dielectric, which allows greater control of the channel in the transistor. This design results in better performance and efficiency of the transistor.

Problems solved by technology

As scaling of complementary metal oxide semiconductor (CMOS) devices continues, control of the channel through conventional means such as doping profile control and gate dielectric scaling becomes increasingly challenging.

Method used

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  • Tapered fin field effect transistor
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first embodiment

[0033]Referring to FIGS. 1A-1C, a first exemplary semiconductor structure according to the present disclosure includes a vertical stack of a handle substrate 10, and an insulator layer 20, and a semiconductor layer 30L.

[0034]The handle substrate 10 can include a semiconductor material, an insulator material, or a conductive material. The handle substrate 10 provides mechanical support to the insulator layer 20 and the semiconductor layer 30L. The handle substrate 10 can be single crystalline, polycrystalline, or amorphous. The thickness of the handle substrate 10 can be from 50 microns to 2 mm, although lesser and greater thicknesses can also be employed.

[0035]The insulator layer 20 includes a dielectric material. Non-limiting examples of the insulator layer 20 include silicon oxide, silicon nitride, sapphire, and combinations or stacks thereof. The thickness of the insulator layer 20 can be, for example, from 100 nm to 100 microns, although lesser and greater thicknesses can also b...

second embodiment

[0070]Referring to FIGS. 9A-9C, a second exemplary semiconductor structure according to the present disclosure can be derived from the first exemplary semiconductor structure by altering the second anisotropic etch. Specifically, a lateral etch that simultaneously removes the material of the etch residue material portions 43 and the semiconductor material of the plurality of semiconductor fins 30 can be employed in lieu of the second anisotropic etch processes employed at the processing steps of FIGS. 3A-3C and 4A-4C. The lateral etch can be an anisotropic etch including an isotropic etch component or an isotropic etch.

[0071]In one embodiment, the removal of the material of the etch residue material portions 43 can be performed such that the sidewall surfaces (and end surfaces) of the plurality of semiconductor fins 30 is performed gradually from bottom to top of the plurality of semiconductor fins 30, and each of the plurality of semiconductor fins 30 has a substantially rectangula...

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PUM

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Abstract

A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Description

BACKGROUND[0001]The present disclosure relates to a semiconductor structure, and particularly to fin field effect transistors including a tapered vertical cross-sectional area and a method of manufacturing the same.[0002]As scaling of complementary metal oxide semiconductor (CMOS) devices continues, control of the channel through conventional means such as doping profile control and gate dielectric scaling becomes increasingly challenging. A few categories of devices such as fin field effect transistors, trigate transistors, and nanowire transistors circumvent the short channel behavior due to scaling.BRIEF SUMMARY[0003]A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap wi...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L29/66
CPCH01L29/66795H01L29/7853H01L21/3065Y02P80/30H01L21/306
Inventor CHANG, JOSEPHINE B.GUILLORN, MICHAEL A.LIN, CHUNG-HSUNMARTIN, RYAN M.SLEIGHT, JEFFREY W.
Owner IBM CORP