Supercharge Your Innovation With Domain-Expert AI Agents!

Ias voltage generator for reference cell and bias voltage providing method therefor

a reference cell and bias voltage technology, applied in static storage, digital storage, instruments, etc., can solve the problems of deterioration of memory cells, read disturb, and longer time length of bias voltage applied to reference cells, so as to achieve effective mitigation

Active Publication Date: 2015-05-07
WINBOND ELECTRONICS CORP
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention is about a device that generates a bias voltage for a reference cell in a flash memory to prevent read-disturbs. The device automatically adjusts the bias voltage when the memory is operating at a low frequency. This helps to improve the reliability and performance of the flash memory.

Problems solved by technology

In the technical field of the related art, when performing a read operation on a serial interface flash memory, a bias voltage applying operation requiring to be performed on a gate of the reference cell would cause an effect of read disturb.
A situation where the bias voltage applying operation is received for a long term commonly leads to deterioration of the memory cell.
Specially, when the serial interface flash memory is operated in a low operation frequency, a time length for the bias voltage applied to the reference cell is longer, and as a result, damages caused to the reference cell would become worse.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Ias voltage generator for reference cell and bias voltage providing method therefor
  • Ias voltage generator for reference cell and bias voltage providing method therefor
  • Ias voltage generator for reference cell and bias voltage providing method therefor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019]With reference to FIG. 1, FIG. 1 is a schematic diagram illustrating a bias voltage generator 100 for a reference cell. The bias voltage generator 100 is adapted to a serial interface flash memory, such as a serial peripheral interface (SPI) flash memory. The bias voltage generator 100 includes a data read detector 110, a cut-off signal generator 120 and an output stage circuit 130. The data read detector 110 receives a sense amplifier enable signal SSAEN and a sense amplifier latch signal SSALAT, which are clock signals in a synchronized clock system, and generates a detection signal DET according to transition points of the sense amplifier enable signal SSAEN and the sense amplifier latch signal SSALAT. The cut-off signal generator 120 is coupled with the data read detector 110. The cut-off signal generator 120 receives and delays the detection signal DET for a time delay to generate a cut-off signal OFFSIG. A start-up time of the cut-off signal OFFSIG is decided according t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The invention is directed to a serial interface flash memory and more particularly, to a bias voltage generator for a reference cell adapted to a serial interface flash memory.[0003]2. Description of Related Art[0004]In the technical field of the related art, when performing a read operation on a serial interface flash memory, a bias voltage applying operation requiring to be performed on a gate of the reference cell would cause an effect of read disturb. The read disturb is relevant to an amount of the voltage level biased by the gate of the reference cell and the length of the bias voltage. Moreover, the read disturb causes reduction of a read margin of the serial interface flash memory, so that the performance of the serial interface flash memory is influenced.[0005]In the technical field of the related art, the bias voltage applied to the reference cell in the serial interface flash memory is sequentially applied to a gate of the re...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): G11C16/28G11C16/32
CPCG11C16/32G11C16/28G11C16/3418
Inventor LIN, HUNG-HSUEH
Owner WINBOND ELECTRONICS CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More