Address Fault Detection Circuit

Abstract

A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,”“false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention is directed in general to word line faults in memories. In one aspect, the present invention relates to address fault detection for integrated circuit memories and associated methods of operation.[0003]2. Description of the Related Art[0004]Integrated circuit memories may fail in a variety of ways, and memory failures can have bigger impact as memories are increasingly used in various computer systems and applications. There are a variety of different ways for a memory to fail, including address decoder faults, word line faults, pre-decoder faults, address latch faults. In the class of memory failures relating to operation of the word lines, one type of fault (called a “no word line select” fault) occurs when no word line is enabled when the memory is intended to be accessed. Detection for this type of failure is commonly indicated by a signal called “word line on indicator” which indicates whether...

AI Technical Summary

Benefits of technology

The present invention relates to detecting and correcting faults in memory systems, particularly addressing word line faults. The invention provides a method and apparatus for quickly and efficiently detecting transient address faults in a multi-bank memory system by using resistive elements or switched word line connection circuits to detect unique voltage levels at a fault detection bit line in each bank caused by address faults. The invention allows for quick and efficient detection of faults, reducing the impact of such errors on the overall performance of the memory system.

Problems solved by technology

Integrated circuit memories may fail in a variety of ways, and memory failures can have bigger impact as memories are increasingly used in various computer systems and applications.

In the class of memory failures relating to operation of the word lines, one type of fault (called a “no word line select” fault) occurs when no word line is enabled when the memory is intended to be accessed.

Another type of fault (called a “multiple word line select” fault) occurs when more than one word line is enabled in the same array.

Yet another type of fault (called a “false word line select” fault) occurs when a word line in an array is incorrectly asserted while another word line is incorrectly deasserted.

For example, transient address faults can be caused by a particle strike in an address decoder, while non-transient address faults can be caused by a physical defect in the memory hardware.

However, address ROM banks require significant chip area, especially when using a multi-bank array architecture with multiple different word lines since every bank needs a ROM bank.

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