Method of forming supra low threshold devices

Abstract

A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate dielectric and formed in a non-volatile memory well region; a first transistor type formed using a first gate oxide and formed in a first transistor well region; a second transistor type formed using a second gate oxide and formed in a second transistor well region; and a third transistor type formed using a third gate oxide and formed in a third transistor well region. The gate dielectric and the first and second gate oxides are formed from the same oxide stack. The first, second, and third transistor types include extension implants formed using a first implant dopant, and the non-volatile memory cell includes extension implants formed using a second implant dopant, where the first and second implant dopants are different.

Description

BACKGROUND[0001]1. Field[0002]This disclosure relates generally to semiconductor devices, and more specifically, to memory cells formed on a same substrate with driver circuitry for the memory cells.[0003]2. Related Art[0004]As semiconductor devices continue to decrease in size and power requirements and performance requirements increase, manufacturers continually seek ways to improve device performance while reducing size and power used by the devices. Devices that operate in different additional power domains may be added, for which transistors having gate sizes that are different from other transistors may be required. While memory cells, low voltage logic devices, and high voltage logic devices can be fabricated on the same substrate, different mask steps are required to form the different devices, including different masks for different gate sizes. For example, adding low voltage logic transistors to a substrate with memory cells and high voltage logic devices can require five ...

AI Technical Summary

Benefits of technology

The present invention provides a method for making a semiconductor device with memory cells and drivers using the same gate oxide but different well and extension implants. This method allows for the construction of low cost devices with good read performance, small die area, lower power and voltage scaling. The method includes forming trench isolation regions in a substrate, forming a first oxide layer, etching the first oxide layer, forming a second oxide layer, implanting well regions, selectively etching the oxide layers, and forming a transistor gate electrode in each region. The method also includes forming extension implants in the non-volatile memory region, the high voltage transistor region, and the low voltage transistor regions. The invention provides a cost-effective solution for manufacturing semiconductor devices with memory cells and drivers on the same substrate.

Problems solved by technology

For example, adding low voltage logic transistors to a substrate with memory cells and high voltage logic devices can require five additional masks, which increases costs and fabrication time.

Yet, if high and low voltage logic devices are formed with the same gate oxide to save mask steps, the low voltage devices will operate slowly, sacrificing speed in favor of lower manufacturing costs.

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