Semiconductor structure and method for manufacturing the same
a technology of semiconductor devices and semiconductor components, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problem of reducing the contact area in conformity with the miniaturization of semiconductor devices
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first embodiment
[0028]FIG. 1 is a view illustrating a semiconductor structure in accordance with a
[0029]Referring to FIG. 1, a semiconductor structure 100 in accordance with a first embodiment may include a first contact structure C1 and a second contact structure C2. The first contact structure C1 and the second contact structure C2 may have different aspect ratios. The aspect ratio refers to a ratio of a height with respect to a width of a given pattern. The given pattern may be a hole pattern or a pillar pattern. For example, the first contact structure C1 and the second contact structure C2 may have the same height as each other and different widths from each other.
[0030]The first contact structure C1 and the second contact structure. C2 may be formed on a semiconductor substrate 101. The semiconductor substrate 101 may include a first doping region 102 and a second doping region 103. The first doping region 102 may be formed in a first region R1, and the second doping region 103 may be formed ...
second embodiment
[0081]The first contact structure C11 according, to the second embodiment, which is a spacer-free structure, may include a silicon region 109, the interface doping region 116, a first metal-silicon region 110, and a first metal region 111. The interface doping region 116 improves a contact resistance between the silicon region 109 and the first metal-silicon region 110. The interface doping region 116 and the silicon region 109 may be the same material. The interface doping region 116 may have a higher concentration than the dopant doped into the silicon region 109. The interface doping region 116 and the silicon region 109 may be doped with the same dopant. The interface doping region 116 may include a polysilicon, in particular, a doped polysilicon. The silicon region 109 may include a doped polysilicon as well.
[0082]FIGS. 4A to 4H illustrates a method for forming the semiconductor structure in accordance with the second embodiment. Except that the semiconductor structure in accor...
third embodiment
[0104]Referring to FIG. 5A, a semiconductor structure 300 in accordance with a third embodiment may include a first transistor Tr1, a second transistor Tr2, first contact structures C1 coupled to the first transistor Tr1, and second contact structures C2 coupled to the second transistor Tr2.
[0105]The first transistor Tr1 may include a first planar gate structure G1 and pair of first doping regions 302. The pair of first doping regions 302 may be respectively positioned in a substrate 301 and at both sides of the first planar gate structure G1. The first contact structures C1 may be coupled to the pair of first doping regions 302, respectively. The first planar gate structure G1 may include a first gate dielectric layer 321A, a first gate electrode 322A, and a first gate cap layer 323A. First gate spacers 324A may be formed on both sidewalls of the first planar gate structure G1. The pair of first doping regions 302 may be source and drain regions of the first transistor Tr1.
[0106]Th...
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