Semiconductor device including shallow trench isolation structures

Abstract

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims the priority of Chinese patent application No. 201410432231.X, filed on Aug. 28, 2014, the entirety of which is incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to semiconductor structures and fabrication processes thereof.BACKGROUND[0003]Shallow trench isolation (STI) structures are commonly used to isolate active regions of semiconductor devices. FIGS. 1-3 illustrates an existing fabrication process of a STI structure.[0004]As shown in FIG. 1, the process includes providing a substrate 100; and forming a trench 101 in the substrate 100. Further, as shown in FIG. 2, the process includes forming an isolation film 102 on surface of the substrate 100; and fills the trench 101. Further, as shown in FIG. 3, the process also includes polishing the isolation film 102 until the surfac...

AI Technical Summary

Benefits of technology

This approach improves the performance of both NMOS and PMOS transistors by managing stress and preventing void formation, thereby enhancing carrier mobility and isolation efficiency in semiconductor devices.

Problems solved by technology

However, such STI structures formed by the HARP may have certain detrimental effects to the semiconductor devices subsequently formed on, and / or in the substrate 100.

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