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Trench confined epitaxially grown device layer(s)

a technology of epitaxial device layer and confined space, which is applied in the direction of semiconductor devices, electrical devices, nanotechnology, etc., can solve the problems of large area growth, difficult epitaxial processes, and unknown techniques and structures worthy of heteroepitaxial device layer manufacturing over silicon substrates

Inactive Publication Date: 2017-06-08
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method and structures for epitaxially growing device layers on silicon substrates, particularly non-planar transistors. The technical effects of the invention include improved channel control and electrical performance of non-silicon materials integrated onto silicon substrates through epitaxial growth of device layers. The method involves a flow chart diagramming the steps involved in the process, while the cross-sections of the patent text show the formation of trench-confined epitaxial device stacks and complementary trench-confined epitaxial device structures. The invention also provides a mobile computing device platform and a functional block diagram of a computing device in accordance with one implementation of the invention.

Problems solved by technology

Such epitaxial processes are challenging at least in part due to lattice mismatch and mismatch in thermal coefficients of expansion (CTE) between the seeding silicon surface and the epitaxially grown semiconductor.
However, techniques and structures worthy of manufacturing heteroepitaxial device layers over silicon substrates are unknown.
For such a technique the seeding silicon substrate has the advantage of being pristine, however such a large area growth can be challenging from a crystal defect standpoint, particularly where there is significant stress induced through thermal expansion or lattice mismatch in the epitaxial film.
While such a technique may not be subject to the same issues particular to large area growths, other issues arise.
For example, the seeding silicon surface may suffer damage and / or become deformed from preliminary processing of the substrate directed at delineating the regions where the epitaxial growth is to occur.
Where a recess etch of the growth substrate (silicon) surface is performed, a bowl or divot shape in the seeding surface may result and subsequently impair epitaxial growth.

Method used

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  • Trench confined epitaxially grown device layer(s)
  • Trench confined epitaxially grown device layer(s)
  • Trench confined epitaxially grown device layer(s)

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Embodiment Construction

[0015]Non-planar transistors employing epitaxially grown device layers and methods to form the same are described. In the following description, numerous details are set forth, however, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to “an embodiment” or “in one embodiment” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable...

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Abstract

Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

Description

[0001]This is a Continuation of application Ser. No. 14 / 302,350 filed Jun. 11, 2014 which is a Divisional of application Ser. No. 13 / 630,527 filed Sep. 28, 2012, which are hereby incorporated by reference.TECHNICAL FIELD[0002]Embodiments of the invention are in the field of semiconductor devices and, more particularly to epitaxially grown device layers.BACKGROUND[0003]Transistors and other semiconductor devices may be fabricated through a number of subtractive and additive processes. Certain benefits, such as channel mobility for transistors, may be had by forming the device layers in semiconductor material other than silicon, such as germanium and III-V materials. Where a crystalline silicon substrate serves as a starting material, epitaxial growth techniques may be utilized to additively form a transistor channel region to integrate such non-silicon materials onto the silicon substrate, typically referred to as heteroepitaxy. Such epitaxial processes are challenging at least in pa...

Claims

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Application Information

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IPC IPC(8): H01L21/84H01L27/12H01L29/78H01L29/423H01L29/66H01L21/02H01L29/06
CPCH01L21/845H01L21/02639H01L27/1211H01L29/0673H01L21/823807H01L29/6681H01L29/6653H01L29/7853H01L29/42392H01L21/8258H01L27/092H01L29/66795H01L29/785H01L29/78696B82Y10/00B82Y40/00H01L29/66439H01L29/775H01L29/66469H01L29/20H01L29/16H01L29/78
Inventor PILLARISETTY, RAVISUNG, SEUNG HOONGOEL, NITIKAVALIEROS, JACK T.DASGUPTA, SANSAPTAKLE, VAN H.RACHMADY, WILLYRADOSAVLJEVIC, MARKODEWEY, GILBERTTHEN, HAN WUIMUKHERJEE, NILOYMETZ, MATTHEW V.CHAU, ROBERT S.
Owner GOOGLE LLC