Semiconductor device, power conversion device, and method of manufacturing semiconductor device
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embodiment 1
[0187]FIG. 30 to FIG. 32 are cross-sectional views of the IGBT, PIN diode, and the RFC diode, each of which is the semiconductor device according to the embodiment 1 of the present invention. Each of FIG. 30 to FIG. 32 is the cross-sectional view along a cross section A2-A2 in the active cell area R1 illustrated in FIG. 4, and illustrates the configuration of the IGBT, the PIN diode, and the RFC diode in the active cell area R1 illustrated in FIG. 1 to FIG. 3. A cross section E-E in FIG. 31 corresponds to the horizontal axis of the depth in FIG. 27 to FIG. 29 described in the principle of present invention. The N− drift layers 14 illustrated in FIG. 30 to FIG. 32 are formed with an impurity concentration ranging from 1.0×1012 to 5.0×1014 cm−3 by using the FZ wafers prepared in the FZ (Floating Zone) method. In the IGBT illustrated in FIG. 30, the junction between the P base layer 9 and the N layer 11 is a main junction. In the PIN diode illustrated in FIG. 31 and the RFC diode illus...
embodiment 2
[0262]Described in the embodiment 2 is a result of the diode performance at a time of applying the various structure parameters and the conditions a) to e) described in the embodiment 1 to the N buffer layer 15 of the RFC diode illustrated in FIG. 32 (FIG. 52 to FIG. 60).
[0263]FIGS. 52 to 54 illustrate an N buffer layer 15 dependence in the snappy recovery operation of the RFC diode of withstand voltage 1200V class. The waveform in the snappy recovery operation at the temperature of −20° C. is as illustrated in FIG. 49. FIGS. 52 and 53 illustrate relationships between an operation temperature of VCC=1000V and Vsnap-off and QRR, respectively. FIG. 54 illustrates a relationship between QRR and VCC at the temperature of −20° C. In FIGS. 52 to 54, the characteristics of the first structure are plotted with black triangles, the characteristics of the second structure are plotted with black circles, and each plotted point is connected by solid line L54 and L55. The characteristics of the ...
embodiment 3
[0276]Described in the embodiment 3 is a result of the diode performance at the time of applying the various structure parameters and the conditions a) to e) described in the embodiment 1 to the N buffer layer 15 of the PIN diode illustrated in FIG. 31(FIG. 61 to FIG. 63).
[0277]The evaluation device whose diode performance is illustrated in FIG. 61 to FIG. 63 is a PIN diode of withstand voltage 4500V class. FIG. 61 to FIG. 63 also illustrates the diode performance of the conventional structures 1 and 2 for comparison, and the impurity profiles of the conventional structures 1 and 2 are already illustrated in FIG. 33. A cross mark in FIG. 61 to FIG. 63 indicates a point at which the device has been broken.
[0278]FIG. 61 illustrates a snappy recovery waveform of the PIN diode at a temperature of 25° C. in the PIN diode of withstand voltage 4500V class. The other switching conditions are VCC=3600V, JF=0.1 JA, dj / dt=280 A / cm2 μs, dV / dt=23000V / μs, and Ls=2.0 μH. A horizontal axis in FIG. ...
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