Determination method and apparatus, program, information recording medium, exposure apparatus, layout information providing method, layout method, mark detection method, exposure method, and device manufacturing method

Abstract

A determination apparatus has a calculation section, where first and second direction pitches intersecting within a predetermined plane of a plurality of detection areas are D1 and D2, respectively, sizes in the first and second directions of each of a plurality of divided areas arranged two-dimensionally along the first and second directions on a substrate are W1 and W2, respectively, and first and second direction pitches of a plurality of marks arranged on the substrate are p1 and p2, respectively, calculates pitch p1 and pitch p2 of the plurality of marks that satisfy formulas (a) and (b) below, based on pitch D1, pitch D2, size W1, and size W2.p1=D1 / i (i denotes a natural number)=W1 / m (m denotes a natural number)   (a)p2=D2 / j (j denotes a natural number)=W2 / n (n denotes a natural number)   (b)

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a continuation of U.S. patent application Ser. No. 16 / 351,081 filed Mar. 12, 2019, which in turn is a continuation of International Application No. PCT / JP2017 / 033376, with an international filing date of Sep. 15, 2017, which claims priority from Japanese Patent Application No. 2016-188889 filed in Japan on Sep. 27, 2016. The disclosure of each of the above-identified prior applications is hereby incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTIONField of the Invention[0002]The present invention relates to a determination method and an apparatus, a program, a layout information providing method, a layout method, a mark detection method, an exposure method, and a device manufacturing method.Description of the Background Art[0003]In a lithography process to manufacture micro-devices such as semiconductors, the devices are formed by overlaying multiple layers of circuit patterns on a substrate (hereinafter gen...

AI Technical Summary

Benefits of technology

This approach enables precise and efficient alignment of marks on a substrate, improving overlay accuracy and reducing costs by optimizing the arrangement of marks and detection areas, thereby enhancing the manufacturing process for micro-devices.

Problems solved by technology

In a lithography process to manufacture micro-devices such as semiconductors, the devices are formed by overlaying multiple layers of circuit patterns on a substrate (hereinafter generally referred to as a wafer) such as wafer or a glass plate, however when the overlay accuracy between the layers is poor, the micro-devices will not be able to exhibit predetermined circuit characteristics and in some cases may be a defective product.

However, the movable alignment detection system has many restrictions on design when compared to a fixed alignment detection system, and was also disadvantageous in terms of cost.

Images