Flash memory device and bit line charging method thereof

Abstract

A flash memory device includes a memory string, a selection switch, a first power source and a second power source. The memory string has a plurality of memory cells. A first memory cell in the memory string is coupled to a first word line, and the first word line is selected to be a programmed word line and the first memory cell is selected to be an inhibited cell, during a first time period, the selection switch is turned on according to a selection signal, and the first power source pulls up voltages on the global bit line and the local bit line to a first voltage. During a second time period, the selection switch is turned-off according to the selection signal, a word line voltage on the first word line is pulled up to pump up the voltage on the local bit line to a second voltage.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention generally relates to a flash memory device, in particular, to a bit line charging method for the flash memory device.2. Description of Related Art[0002]In a conventional NAND flash memory is organized into a plurality of blocks, which are programmable and erasable. For providing signals with higher voltage, some charge pump circuits are needed to be disposed on-chip. The charge pump circuits occupy chip area and thereby increases chip size and cost. Thus, the flash memory devices suffer inefficiencies power resulting from their operation schemes in low power system. Also, an exposure of unselected memory cell should not be programmed in a program sequence. A bit line voltage should be well set to inhibit a memory cell which is not programmed.SUMMARY OF THE INVENTION[0003]The present invention provides a flash memory device and a bit line charging method thereof for well inhibiting a memory cell which is ...

AI Technical Summary

Benefits of technology

The present patent provides a way to program flash memory cells using a single power source to pull up the voltages on both the local and global bit lines at the same time. By turning off the connection between the two lines, the memory cell can be inhibited by pumping up the voltage on the local bit line to a higher level. This method eliminates the need for an extra power source and reduces circuit size while improving efficiency.

Problems solved by technology

That is, the flash memory device in presented disclosure needs not provide an extra power source to generate the higher voltage.

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