Fdsoi device structure and preparation method thereof

Abstract

An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 Å; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims priority to Chinese patent application No. CN 202010992691.3, filed on Sep. 21, 2020 at CNIPA, and entitled “FDSOI DEVICE STRUCTURE AND PREPARATION METHOD THEREOF”, the disclosure of which is incorporated herein by reference in entirety.TECHNICAL FIELD[0002]The present application relates to the field of semiconductor technologies, in particular to an FDSOI device structure and a preparation method thereof.BACKGROUND[0003]Currently, in the advanced note such as 22 nm, the PMOS devices for Fully Depleted Silicon-on-Insulator (FDSOI) generally adopt a silicon channel-metal gate process, where the channel is a silicon channel and the gate is a high-k metal gate. The channel in this process is a silicon channel, and the compressive stress in the channel needs to be increased. Therefore, in order to increase the compressive stress in the channel, the silicon channel is replaced with a silicon germanium (SiGe) channel, ...

AI Technical Summary

Benefits of technology

The FDSOI device and fabrication method of this patent application have a few benefits. First, the device has a channel made up of a SiGe layer and silicon epitaxial layer, which reduces stress and prevents the diffusion of Ge into the gate dielectric, resulting in better reliability and performance for the device.

Problems solved by technology

However, the germanium in the SiGe channel in the current technology may diffuse into the gate dielectric, thereby reducing reliability and performance of the PMOS devices.

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