Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting

Abstract

A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in / stress. Also provided is a method for implementing the wafer level product burn-in / screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the contacting of any wafer. More particularly, the invention also relates to method for implementing the wafer level product burn-in / screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system.In order to reduce the extent of any reliability failure rate which may be encountered during the early life of integrated circuits, semiconductor VLSI / ULSI products are usually subjected to burn-in or temperature / voltage screens that are designed to screen out any present or potential failures due to manufacturing defects, which otherwise may occur at an early time during field operations. The burn-in is normally carried out at the packaged level of individual product chips, whereby each product wa...

AI Technical Summary

Benefits of technology

This approach reduces costs and time by allowing for simultaneous burn-in and reliability evaluations of all chips on a wafer, improving efficiency and reducing the need for custom equipment, while maintaining control over stress conditions for various failure mechanisms.

Problems solved by technology

Although a considerable amount of investigative work has been carried out in the technology in connection with wafer level burn-in, particularly for all chips simultaneously, the current state-of-the-technology still does not clearly provide for a unique and advantageously implementable wafer level system analogous to that disclosed by the present invention.

All of the concepts used for this prior art require complicated systems with difficult requirements of tolerances, thermal properties and matching properties.

Also, these prior art publications would not be satisfactory for very high frequency chip technology because of the need for additional off chip contacting fixtures.

It should be noted, however, that those prior art publications are primarily for initial device characterization and measurements, and not for burn-in, voltage screen, or reliability evaluations of failure mechanisms.

That system, however, cannot be used for fully processed and integrated wafers with metal levels because the lateral transport of atomic hydrogen in metal-oxide-semiconductor capacitors with aluminum or polysilicon gates is extremely limited.

Also the technique can not be used for evaluation of other reliability failure mechanisms such as hot carriers, electromigration and bias temperature stability.

It also cannot be used for burn-in of product chips.

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