Metal-oxide-semiconductor device including a buried lightly-doped drain region

Abstract

An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to semiconductor devices, and more particularly relates to a metal-oxide-semiconductor (MOS) device having a lightly-doped drain (LDD) region configured for providing improved high-frequency performance.BACKGROUND OF THE INVENTION[0002]Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In conventional LDMOS devices, which typically include an LDD region, the LDD region is often formed at or near an upper surface interface between the silicon and oxide of the device. Locating the LDD region in close relative proximity to the silicon / oxide interface, however, significantly increases the likelihood that ionized carriers will become trapped at the interface, thereby resulting in undesirable hot carrier degradation (HCD) in the device.[0003]HCD in an MOS device gene...

AI Technical Summary

Benefits of technology

[0007]The present invention provides techniques for reducing the on-resistance of an MOS device without significantly increasing HCD and / or the gate-to-drain capacitance in the device, thereby improving a high-frequency performance and reliability of the device. Moreover, the techniques of the present invention can be used to fabricate an integrated circuit (IC) device, for example, an LDMOS device, using conventional CMOS-compatible process technology. Consequently, the cost of manufacturing the IC device is not significantly increased.

[0008]In accordance with one aspect of the invention, an MOS device is formed including a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region. In this manner, the LDMOS device exhibits improved high-frequency performance, and is also substantially compatible with a CMOS process technology.

Problems solved by technology

Consequently, the cost of manufacturing the IC device is not significantly increased.

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