Microcomputer that cooperates with an external apparatus to be driven by a drive signal
a microcomputer and drive signal technology, applied in the field of microcomputers, can solve the problems of large large amount of power consumption of the microcomputer, and noise canceling process, etc., and achieve the effect of reducing power consumption, excellent noise-free characteristic, and reducing power consumption
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first embodiment
[0059]The microcomputer 2 comprises an intermittent operation control section 150 and a level detecting circuit 170. The intermittent operation control section 150 is structured to input a rise request WD from the level detecting circuit 170 in addition to the intermittent operation control section 150 of the The level detecting circuit 170 operates depending on a command from the CPU 3 to perform, for every constant period, the process to read the signal level via an I / O port 70 from a terminal of the microcomputer 2. The intermittent operation control section 150 and level detecting circuit 170 operate by receiving a sub-clock which is always generated from a sub-oscillation circuit 19. The level detecting circuit 170 corresponds to the automatic signal reading means and the oscillation control section 11 and intermittent control section 150 correspond to a timer rise control means.
[0060]The CPU 3 can stop the operation thereof by executing a particular operation stop instruction...
third embodiment
[0087]A third embodiment will be explained with reference to FIG. 9 and FIG. 10. The elements similar to those of above embodiments are designated by the like reference numerals. In FIG. 10, an ECU 100 provided with a communication function comprises the one-chip type microcomputer 2 and an external apparatus 50 including the communication function. The microcomputer 2 is provided, in addition to the elements of above embodiments, with an intermittent operation control section 151 for intermittently operating the CPU 3 and a timer interlocking control section 120 for outputting a drive signal RQ to the external apparatus 50 conforming to an instruction from the CPU 3. An oscillation control section 110, the intermittent operation control section 151 and timer interlocking control section 120 are operated by receiving a sub-clock which is always generated from the sub-oscillation circuit 19. The CPU 3 outputs, with a stop means 3n, the operation command SD to the intermittent operati...
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