Semiconductor device with a rewiring level and method for producing the same

Abstract

A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of PCT / DE2004 / 001853, filed Aug. 19, 2004, and titled “Semiconductor Device With a Rewiring Level and Method for Producing the Same,” which claims priority to German Application No. DE 103 39 762.0, filed on Aug. 27, 2003, and titled “Semiconductor Device With a Rewiring Level and Method for Producing the Same,” the entire contents of which are hereby incorporated by reference.FIELD OF THE INVENTION[0002]The present invention relates to a semiconductor device with a plastic package, with at least one semiconductor chip and with a rewiring level, and also to a method for producing the same.BACKGROUND[0003]Graphic memory devices are ahead of standard memory devices in terms of their electrical requirements. With desired clock frequencies in the gigahertz range, high speeds are expected in the semiconductor chips, unattainable with conventional bonding pad arrangements in the form of rows of signal contact ...

AI Technical Summary

Benefits of technology

The solution significantly reduces inductive impedance, enabling operation at gigahertz clock frequencies and meeting DDR-III requirements, while ensuring high performance and low transit time differences for DDR-II memory devices, even when stacking identical semiconductor chips.

Problems solved by technology

With desired clock frequencies in the gigahertz range, high speeds are expected in the semiconductor chips, unattainable with conventional bonding pad arrangements in the form of rows of signal contact areas in a central bonding channel, especially since the long rewiring lines from the central bonding channel to the peripheral sides of the memory chips have excessively high inductance values, which increase the impedance and reduce the clock frequencies.

These disadvantages have even more horrendous effects when it is attempted to stack such semiconductor chips of an identical type.

For rapid access to memory data of the semiconductor chips with clock frequencies in the gigahertz range, as in the case of DDR-II (Double Data Rate II) or DDR-III (Double Data Rate III) memory chips, chip stacks are not suitable.

The stacking has the effect that such semiconductor devices with a semiconductor chip stack do not achieve the “high performance” criteria for DDR-II or DDR-III memory devices and therefore have until now only allowed themselves to be stacked by sacrificing “high performance”, which leads to unacceptable values with respect to the criteria of DDR-II devices.

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