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Method of fabricating vertically aligned group III-V nanowires

a technology of nanowires and vertical alignment, which is applied in the field of compound semiconductor micro/nanowire arrays, can solve the problems of narrow growth conditions of grown nanowires, higher impurities and point defect densities, and lower growth temperatures

Active Publication Date: 2014-11-25
NAT TECH & ENG SOLUTIONS OF SANDIA LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The method produces nanowires with improved crystalline quality, reduced defects, and enhanced performance by removing plasma etch damage, leading to higher internal quantum efficiency and longer lifespan of nanowire-based devices like LEDs.

Problems solved by technology

Metal catalyzed-grown nanowires also require narrow growth conditions which involves lower than optimal growth temperatures.
These growth conditions may introduce higher impurities and point defect densities than the conditions used for creating commercial-quality planar LEDs and provide less flexibility for adjusting growth parameters to optimize doping concentrations and other desired material properties.
However, the top-down plasma etching leads to damaged, rough, and non-faceted sidewalls with defects, and leakage currents that limits performance.

Method used

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  • Method of fabricating vertically aligned group III-V nanowires
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  • Method of fabricating vertically aligned group III-V nanowires

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Embodiment Construction

[0020]The present invention is directed to a method of fabricating vertically aligned Group III-V micro- or nanowires. The method comprises providing a Group III-V substrate or at least one Group III-V layer on a growth substrate; coating the top surface of the Group III-V substrate or layer with an etch mask; anisotropically etching (e.g., via dry etching) the Group III-V substrate or at least one layer through the etch mask and removing the etch mask to provide an array of nanowires; and selectively wet etching the sidewalls of the nanowires to remove anisotropic etch damage and provide an array of vertically aligned Group III-V nanowires. The nanowires can have a variety of cross sections depending on the etch chemistry, including circular. The wire diameters and lengths can be controlled by the etch times. The method is scalable from nanowire cross-sectional dimension (e.g., diameter) of approximately 5 nm to 100 microns. Therefore, the terms microwire, nanowire, and micro / nanow...

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Abstract

A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro / nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 588,446, filed Jan. 19, 2012, which is incorporated herein by reference. This application is related to U.S. application Ser. No. 13 / 434,646, filed Mar. 29, 2012, and SD12195, titled “Amber Light-Emitting Diode Comprising a Group III-Nitride Nanowire Active Region,” filed of even date with this application, both of which are incorporated herein by reference.STATEMENT OF GOVERNMENT INTEREST[0002]This invention was made with Government support under contract no. DE-AC04-94AL85000 awarded by the U.S. Department of Energy to Sandia Corporation. The Government has certain rights in the invention.FIELD OF THE INVENTION[0003]The present invention relates to compound semiconductor micro / nanowire arrays and, in particular, to a top-down method of fabricating vertically aligned Group III-V micro- and nanowires.BACKGROUND OF THE INVENTION[0004]Improving the performance of Gro...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L33/04H01L21/00B82Y40/00
CPCB82Y40/00H01L33/04H01L33/18H01L33/24Y10S977/762B82Y30/00
Inventor WANG, GEORGE T.LI, QIMING
Owner NAT TECH & ENG SOLUTIONS OF SANDIA LLC