Horizontal gate all around and FinFET device isolation

Abstract

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims benefit to U.S. Provisional Patent Application No. 62 / 159,715, filed May 11, 2015 and to U.S. Provisional Patent Application No. 62 / 265,260, filed Dec. 9, 2015, both of which are hereby incorporated herein by reference in their entirety.BACKGROUND[0002]Field[0003]Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments described herein relate to horizontal gate all around device structures and fin field effect transistor device structures. Further embodiments relate to methods for forming horizontal gate all around device structures and fin field effect transistor device structures.[0004]Description of the Related Art[0005]As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structure to improve electrostatic coupling and reduce negative effects such...

AI Technical Summary

Benefits of technology

This patent describes a device structure which includes a superlattice structure formed on a substrate. The superlattice structure includes layers of silicon material, silicon germanium material, and a buried oxide layer arranged in a stacked arrangement. By including the superlattice structure, the device has improved performance and stability. The device structure can be used in various electronic devices such as logic circuits and memory cells. The technical effect is to provide a more efficient and reliable device structure for various electronic applications.

Problems solved by technology

However, challenges associated with hGAA structures include the existence of a parasitic device at the bottom of the stacked lattice matched channels.

FinFET structures, which may exhibit different architectures from hGAA structures, also suffer from parasitic leakage and capacitance.

However, a dosage of the dopants required to suppress the leakage may hinder epitaxial growth of device structures on the parasitic device.

The dopants may deleteriously diffuse into channels of the device structures during subsequent processing operations, which may result an undesirable increase in device variability.

In addition, implantation may not adequately reduce parasitic capacitance.

However, thermal oxidation processes generally require temperatures beyond the thermal budgets of the stacked lattice matched channels.

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