Method for measuring silicon slice extension linear defect
A linear defect and measurement method technology, applied in semiconductor/solid-state device testing/measurement, etc., can solve problems such as differences in operators, long time spent, damage to silicon wafers, etc.
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[0014] The present invention will be described in further detail below in conjunction with the accompanying drawings.
[0015] The present invention is based on the principle that when the epitaxy temperature distribution of the silicon wafer is unbalanced, linear defects will be generated at the horizontal or vertical positions between the silicon wafer and the notch, and will grow when the linear defect (Slip) is generated at the defect. The accumulated stress is released, and when there is a sudden change in the absolute value of the stress, there must be a linear defect (Slip); therefore, it can be considered that the stress measurement instrument can be used for a given process (given growth temperature, pressure, gas flow, etc.) The growing epitaxy is subjected to stress measurement, and based on this, it is judged whether there is a defect, and the defect is sensed and managed.
[0016] The method provided by the present invention is carried out according to the followi...
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