Making method of semiconductor memory part

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as difficult control of the width of sidewall spacers

Active Publication Date: 2009-03-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0006] Therefore, the object of the present invention is to provide a kind of manufacturing method of semiconductor memory device, and this method controls sidewall spacer layer by carrying out adaptive adjustment (season) and strict control etching time to reaction chamber when forming sidewall spacer layer. to solve the problem that the width of the sidewall spacer in the prior art is difficult to control

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  • Making method of semiconductor memory part
  • Making method of semiconductor memory part
  • Making method of semiconductor memory part

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Embodiment Construction

[0031] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0032] The invention discloses a manufacturing method of a semiconductor gate structure, which has high control precision for the width of the sidewall spacer layer of the SONOS device of 90nm or less.

[0033] The CMOS process has entered the process node below 90nm, and it is becoming more and more important to control the width of the sidewall spacer and its variation. Changes and / or large changes in the width of the sidewall spacers will lead to significant changes in the saturation leakage current of NMOS and PMOS devices, thereby affecting device performance. In the process node below 90nm, the width of the sidewall spacer is controlled at 85 about. The present invention adopts high dielectric constant material such as silicon...

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Abstract

The invention discloses a manufacturing method of a semiconductor device, after periodically maintaining a reaction chamber, the method comprises: peforming adaptability adjustment on the reaction chamber by a test wafer; solely executing an etching process in the reaction chamber by the test wafer; detecting an etching speed; adjusting an etching process time for formally producting wafers according to the etching speed. The method of the invention is capable of controlling a lateral wall interlayer in a desired width, the error is controlled in a range of + / -1, and an adaptability adjustment time desired after periodically maintaining the reaction chamber is reduced, production efficiency and nondefective rate are increased, production cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a spacer (offset spacer) with an isolation function in a SONOS (silicon-oxide-nitirde-oxide-silicon) storage device manufacturing method. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards higher component density and high integration. In semiconductor storage devices such as DRAM, SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride-oxide-silicon) storage devices are a new generation of low-voltage, high-density non-volatile semiconductor flash memory devices, with Its excellent scaling characteristics are widely used. The core structure of the SONOS device is an oxide-nitirde-oxide ONO stacked dielectric layer structure formed between th...

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L21/311H01L21/336
Inventor张海洋张世谋马擎天刘燕丽
OwnerSEMICON MFG INT (SHANGHAI) CORP