Multiple step grating structure and its producing method

Abstract

Multilayer staircase type grid structure includes semiconductor base plate in multilayer staircase structure (MSS), grid oxide layer setup on MSS, and conductive layer setup on the grid oxide layer. It will be better that grid oxide layers on each surface of staircase in MSS possess different thickness. In addition, multilayer staircase type grid structure includes multiple doping sections with different doping densities setup in semiconductor base plate in low part of MSS. Different doping material and doping dose are adopted for preparing each doping area in doping area. The thickness of the grid oxide layer and starting up voltage of multilayer staircase type grid structure are controllable. Whole length of carrier channel in multilayer staircase type grid structure is equal to summation of width and height of MSS so as to solve short-channel effect effectively.

Description

technical field [0001] The invention relates to a multi-step gate structure and a preparation method thereof, in particular to a multi-step gate structure for increasing the carrier channel length of a transistor through a multi-layer ladder structure of a semiconductor substrate and a preparation method thereof. Background technique [0002] figure 1 It is a well-known metal oxide semiconductor field effect transistor 10 (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET). The transistor 10 is mainly composed of a gate 20 (consisting of a semiconductor substrate 12, a gate oxide layer 14 and a metal conductive layer 16) and two doped regions 18 arranged in the semiconductor substrate 12 on both sides of the gate 20 (as transistors). drain and source). In addition, the transistor 10 further includes a silicon nitride spacer 22 disposed on the sidewall of the gate 20 for electrically isolating the gate 20 . [0003] Although figure 1 The transistor 10 shown has be...

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Problems solved by technology

[0003] Although figure 1 The transistor 10 shown has been widely used in integrated circuits. However, with the continuous improvement of the integration level of semiconductor technology and the continuous shrinking of device dimensions, the size of the traditional transistor 10 and the length of the carrier channel are also relatively reduced, resulting in the above-mentioned The two doped regions 18 interact with a carrier channel 24 disposed below the gate 20 to affect the switching control capability of the gate 20 to the carrier channel 24, which results in the so-called short channel effect (short channel effect). channel effect)

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