Integrated surface plasma wave generator
A surface plasmon wave and generator technology, applied in the field of integrated optoelectronics, can solve the problems of poor stability, large volume, difficult adjustment, etc., and achieve the effect of good stability
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Embodiment 1
[0025] The basic structure of the integrated surface plasmon wave generator of the present invention is as Figure 5 shown. Select an n-type InP substrate 81, on which a 2 μm thick n-type InP buffer layer 82 is grown; a 50 nm thick InGaAsP etch stop layer 92 is sandwiched between an InGaAsP MQW active layer 91 with a wavelength of 1.5 μm In the middle of the InGaAsP waveguide layer 93 , the thicknesses of the upper and lower waveguide layers are 30 nm and 100 nm respectively; after that, a 2 μm p-type InP cladding layer 83 is grown. A photoresist with a thickness of 100 nm is coated as an etching stop mask 10 in a region of 300 μm wide on the upper surface of InP. Carry out dry etching to the part outside mask, the purpose of etching is to be used for forming plasma waveguide part, etching will stop at etching stop layer 92 places, sputter Au thin film 31 (50nm) on it; Then The mask 10 is removed, and the positive and negative electrodes 11 are sputtered on the upper and low...
Embodiment 2
[0027] Another embodiment of the present invention is structured as Figure 6 shown. Select an n-type GaAs substrate 121, on which a 2 μm thick n-type GaAs buffer layer 122 is grown; a 50 nm thick GaInP etch stop layer 132, an AlGaInP MQW active layer 131 with a wavelength of 650 nm is sandwiched between the AlGaInP waveguide layer 133 In the middle, the thickness of the upper and lower waveguide layers is 100 nm; after that, a 2 μm p-type GaAs cladding layer 123 is grown. A photoresist with a thickness of 100 nm is coated as an etching stop mask 10 in a region of 300 μm wide on the GaAs upper surface. Carry out dry etching to the part outside mask, the purpose of etching is to be used for forming plasma waveguide part, etching will stop at etching stop layer 132 place, sputter Au thin film 31 (50nm) on it; Then The mask 10 is removed, and the positive and negative electrodes 11 are sputtered on the upper and lower surfaces of the device. After a bias current is applied thr...
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