Unlock instant, AI-driven research and patent intelligence for your innovation.

Solid-state circuit assembly

A circuit device and semiconductor technology, which is applied in the manufacturing of semiconductor devices, circuits, and semiconductor/solid-state devices, etc., can solve problems such as the adverse effects of existing layout corrections and the decrease of integrated concentration.

Inactive Publication Date: 2009-04-29
INFINEON TECH AG
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] However, the disadvantage in this case is that the higher bulk concentration actually seen in this approach is at least partially rejected again
[0014] This sequence has detrimental effects on circuit design and modification of existing layouts, so existing layouts cannot be immediately converted to the next shrinkage drop or the next bulk density drop

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Solid-state circuit assembly
  • Solid-state circuit assembly
  • Solid-state circuit assembly

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0028] in accordance with Figure 3A and Figure 3B The semiconductor substrate 1 having at least one first doped region of the first conductivity type p also includes a second doped region 2 of the second conductivity type n opposite to the first conductivity type p. Furthermore, the highly doped connection doped region 3 of the second conductivity type n is sequentially placed in the second doped region 2 to connect this region, creating an ohmic junction with the second doped region 2 . The conductive structure to be planarized is at least partially embedded and one or more insulating layers 6 are formed on the surface of the semiconductor substrate 1 in contact with the connecting doped region 3 . The conductive structure in this example is a contact hole or aperture 4 that is filled with a conductive substance, and an interconnection layer 5 that is electronically connected thereto.

[0029] In order to implement the interconnection layer 5 , it is preferred to implement...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a semiconductor circuit device, comprising a semiconductor substrate (1), a first doped region, a second doped region (2), a connecting doped region (3), and an insulating layer (6) , a conductive structure (4, 5) to be planarized, the charge carriers formed during the planarization step are doped by discharges formed in the first and second doped regions (1, 2) The heterogeneous regions (7) are reliably dissipated and dendrite formation is avoided.

Description

technical field [0001] The present invention relates to semiconductor circuit devices, and in particular to semiconductor circuit devices that avoid the formation of dendrites during the planarization step. Background technique [0002] After the integrated semiconductor circuit, a higher bulk concentration appeared, which led to the reduction of the characteristic size of the semiconductor material, especially the reduction of the characteristic width of the conductive structure. To date these conductive structures have been preferably deposited by aluminum layers in corresponding wiring levels to create interconnections, followed by patterning by photolithography, a traditional method characterized by quantifiable limitations and lack of mobility properties which are no longer used. Current and future interconnect structures. [0003] Therefore, alternative materials and methods are gradually being used, especially for the metallization layer characteristics to meet the i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/06H01L21/768H01L29/417
CPCH01L29/0615H01L21/7684H01L29/417
Inventor G·布拉塞M·奥斯特马耶E·鲁德尔
Owner INFINEON TECH AG