Chip encapsulation structure

Abstract

The invention discloses a chip encapsulating structure, which comprises a carrier, a chip, a plurality of the first bond wires, a plurality of the second bond wires and an encapsulating colloid, wherein the carrier has a plurality of the first joints and at least one second joint, and the chip has at least one first pad and at least one second pad. Besides, the first bond wires are electrically connected with the first pads and the first joins, while the second bond wires are electrically connected with the second pads and the second joints, wherein the first pad is electrically connected with at least two first joints via at least two first bond wires, while the second pad is electrically connected with one second joint via one second bond wire. Besides, the encapsulating colloid is equipped on the carrier to wrap the chip, a plurality of the first bond wires and a plurality of the second bond wires.

Description

technical field [0001] The present invention relates to a chip package structure (Chip package structure), in particular to a wire bonding (Wire bonding) chip package structure. Background technique [0002] In recent years, with the rapid development of electronic technology and the rise of the semiconductor industry, electronic products that are more humane and better in function are constantly being introduced, and are designed towards the trend of light, thin, short and small. In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) is mainly divided into three stages: integrated circuit design, integrated circuit manufacturing, and integrated circuit packaging (package). In the packaging of integrated circuits, the bare chip is first completed through the steps of wafer fabrication, circuit design, photomask fabrication, and wafer cutting, and each bare chip formed by wafer cutting is passed through the bare chip The bonding pad on...

AI Technical Summary

Problems solved by technology

However, the contacts 112a and 112c are respectively disposed on the carrier 110 and correspond to the two sides of the chip 120, that is, the wire 104 has a more difficult layout circuit than the wire 102.

In other words, the wire 104 is more likely to be broken or a wrong situation occurs in the circuit layout, so that the bearing seat 110 cannot be used.

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