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Storage for controlling address buffer by programmable delay

A memory and buffer technology, applied in the field of programmable delay, can solve the problems of cycle time increase, energy consumption, loss, etc., and achieve the effect of reducing power consumption and eliminating timing differences

Inactive Publication Date: 2010-02-03
VLSI TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Choosing a timing period that is too short can cause significant losses in the manufacturing process
Choosing a timing period that is too long can result in a noticeable increase in cycle time and unnecessary energy consumption
[0005] The situation is even worse when trying to generate independent control signals for detecting dynamic amplifiers since there is no tracking mechanism between address reset and dynamic amplifier activation

Method used

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  • Storage for controlling address buffer by programmable delay
  • Storage for controlling address buffer by programmable delay
  • Storage for controlling address buffer by programmable delay

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Embodiment Construction

[0017] figure 1 is a block diagram of a representative portion of memory device 100 implemented in accordance with the present invention. Memory device 100 may be implemented in any type of integrated circuit (IC) or package known to those skilled in the art. The memory device 100 shown is an eight (8) megabit write hysteresis synchronous static RAM (SRAM) device operating at approximately 333 MHz. However, it should be understood that the present invention is applicable to any type of memory device of any size and speed.

[0018] Address buffer 102 is provided with a plurality of address bits (ADDR j , the address buffer 102 asserts a plurality of address signals A corresponding to the predecoder 104 j and address complement signal AB j . Predecoder 104 asserts several sets of address signals, including block selection address signal A B , row address signal A R , and the column address signal A C . Denoted jointly by K R / W One or more read / write (R / W) clock signals...

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PUM

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Abstract

A memory utilizing programmable delay circuits to control address buffers is disclosed. A programmable delay circuit is provided for each block of the memory device. Each of the delays within each block is programmed by a global fuse circuit. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. The global fuse circuit used to program the delay device within each of the blocks is also used to program the delay device within the clock control circuit so that the program delay within the clock control circuit and the data blocks are essentially the same.

Description

technical field [0001] The present invention relates to memory systems, and more particularly to programmable delays for generating a reset signal to an address buffer for a zeroing scheme to improve speed and reduce power. Background technique [0002] Dynamic detection is commonly used to detect small bit line differences in certain types of memory systems. For example, synchronous random access memory (SRAM) typically uses dynamic detection. Dynamic detection is typically implemented with a dynamic amplifier that must be precharged before the next detection event. Therefore, a reset signal is required to precharge the dynamic amplifier in preparation for subsequent detection events. A common method used to generate a reset signal is to zero all addresses, also known as a return-to-zero (RTZ) scheme. This reset signal is used to reset all predecoders and dynamic sense amplifiers. In a typical RTZ scheme, each address buffer asserts two signals, the true address signal ...

Claims

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Application Information

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IPC IPC(8): G11C11/4063G11C11/413G11C7/00G11C8/00G11C8/06G11C8/18H03K5/13
CPCG11C8/06G11C8/18G11C8/00
Inventor 威廉·罗伯特·韦尔常瑞格林·斯塔尼斯
Owner VLSI TECH LLC