A test structure and method for detecting charge effects using a delayed inversion point technique

Abstract

A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.

Description

technical field [0001] The present invention generally relates to the testing and analysis of processes used to manufacture integrated circuit components, and more particularly to the measurement and monitoring of charge states in test structures of gate dielectric layers during semiconductor process steps. Background technique [0002] The fabrication of large integrated circuits involves hundreds of discrete process steps. These steps are typically divided into two sub-steps. The first of these sub-steps is often referred to as the front-end process, during which semiconductor elements are formed in a silicon wafer. The second sub-step is generally referred to as the back-end process, during which various metal connection layers and contacts are formed on the semiconductor devices formed in the front-end process sub-step. [0003] The front-end and back-end processes include many sub-process steps that involve deposition of material, patterning of layers by lithography, ...

AI Technical Summary

Problems solved by technology

This insufficient capacitance change would render known CV methods useless for monitoring state of charge

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